Browse "College of Engineering(공과대학)" by Author Ryu, Seung-Tak
Showing results 1 to 60 of 183
| 1-bit and multi-bit envelope delta-sigma modulators for CDMA polar transmitters K., Woo-Young; Ki-Young K.; Ryu, Seung-Tak; Jae-Kil J.; Park, Chul Soon, 2008 Asia Pacific Microwave Conference, APMC 2008, IEEE, 2008-12-16 |
| A 0.014mm2 9b switched-current DAC for AMOLED mobile display drivers Kim, H.-S.; Jeon, J.-Y.; Lee, S.-W.; Yang, J.-H.; Ryu, Seung-Tak; Cho, Gyu-Hyeong, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, pp.316 - 317, IEEE, 2011-02-20 |
| A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI- SAR) ADC Kim, Wan; Hong, Hyeok-Ki; Roh, Yi-Ju; Kang, Hyun-Wook; Hwang, Sun-Il; Jo, Dong Shin; Chang, Dong-Jin; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1826 - 1839, 2016-08 |
| A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section Kim, Jong Pal; Lee, Wonseok; Suh, Junyeub; Lee, Hyungwoo; Lee, Kyuil; Ahn, Ho Young; Seo, Min-Jae; et al, 42nd Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC), pp.4012 - 4015, IEEE, 2020-07 |
| A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications Oh, Ghilgeun; Lee, Chang-Kyo; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.61, no.1, pp.6 - 10, 2014-01 |
| A 10-bit 50-MS/s pipelined ADC with opamp cuffent reuse Ryu, Seung-Tak; Song, BS; Bacrania, K, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.42, pp.475 - 485, 2007-03 |
| A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs Kim, Hyun Sik; Yang, Jun-Hyeok; Park, Sang Hui; Ryu, Seung-Tak; Cho, Gyu-Hyeong, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.3, pp.766 - 782, 2014-03 |
| A 10b 50MS/s pipelined ADC with opamp current reuse Ryu, Seung-Tak; Song, Bang-Sup; Bacrania, Kanti, IEEE, pp.216 - 217, 2006-02 |
| A 10b linear interpolation DAC using body-transconductance control for AMLCD column driver Park, C.; Kim, K.-D.; Lee, S.-W.; Park, G.-S.; Ryu, Seung-Tak; Cho, G.-H., 2010 6th IEEE Asian Solid-State Circuits Conference, pp.165 - 168, IEEE, 2010-11-08 |
| A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration Park, Chang Un; Chung, Jaehyun; Ryu, Seung-Tak, 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023, IEEE, 2023-04-26 |
| A 14-b linear capacitor self-trimming pipelined ADC Ryu, Seung-Tak; Ray, S; Song, BS; Cho, Gyu-Hyeong; Bacrania, K, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.39, pp.2046 - 2051, 2004-11 |
| A 14b-linear capacitor self-trimming pipelined ADC Ryu, Seung-Tak; Ray, S.; Song, B.-S.; Cho, G.-H.; Bacrania, K., Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference, v.47, pp.464 - 0, 2003-02-15 |
| A 15 mu m-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory Jin, Dong-Hwan; Kwon, Ji-Wook; Kim, Hyeon-June; Hwang, Sun-Il; Shin, Mincheol; Cheon, Junho; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.10, pp.2431 - 2440, 2015-10 |
| A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-mu m CMOS Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Hwang, Sun-Il; Kim, Jong-Pal; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.11, pp.3617 - 3627, 2018-11 |
| A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-um CMOS Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Hwang, Sun-Il; Kim, Jong-Pal; Ryu, Seung-Tak, International Symposium on Integrated Circuits and Systems, pp.3617 - 3627, IEEE CAS Society, 2018-09-02 |
| A 180-mu W, 120-MHz, Fourth Order Low-Pass Bessel Filter Based on FVF Biquad Structure Shin, Hundo; Ryu, Seung-Tak, IEICE TRANSACTIONS ON ELECTRONICS, v.E95C, no.5, pp.949 - 957, 2012-05 |
| A 2.6b/cycle-Architecture-Based 10b 1.7GS/s 15.4mW 4x-Time-Interleaved SAR ADC with a Multistep Hardware-Retirement Technique Hong, Hyeok-Ki; Kang, HW; Jo, DS; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25 |
| A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs Hwang, Sun-Il; Chung, Jaehyun; Kim, Hyeon-June; Jang, Il Hoon; Seo, Min-Jae; Cho, Sang-Hyun; Kang, Heewon; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.3, pp.1119 - 1126, 2018-03 |
| A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS Sung, BRS; Jo, DS; Jang, IH; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25 |
| A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-order SARAssisted CT DSM with 1-0 MASH and DNC Lozada, Kent Edrian; Lee, Dong-Hun; Kim, Ye Dam; Kim, Ho-Jin; Cho, Youngjae; Choi, Michael; Ryu, Seung-Tak, 2023 IEEE Asian Solid-State Circuits Conference, IEEE, 2023-11-08 |
| A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration Chang, Dong-Jin; Choi, Michael; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.9, pp.2691 - 2700, 2021-09 |
| A 4(th)-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling Lozada, Kent Edrian; Jang, Il-Hoon; Bae, Gyeom-Je; Lee, Dong-Hun; Kim, Ye-Dam; Lee, Hankyu; Kim, Seong Joong; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.69, no.9, pp.3635 - 3639, 2022-09 |
| A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling Jang, Il Hoon; Seo, Min-Jae; Cho, Sang-Hyun; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sunwoo; Choi, Michael; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1139 - 1148, 2018-04 |
| A 4.2mW 10MHz BW 74.4dB SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC Jang, Il-Hoon; Seo, Min-Jae; Kim, Mi-Young; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sun-Woo; Choi, Michael; et al, Symposium on VLSI Circuits, pp.C34 - C35, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-06 |
| A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting Im, Jong-Pil; Wang, Se-Won; Ryu, Seung-Tak; Cho, Gyu-Hyeong, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.47, no.12, pp.3055 - 3067, 2012-12 |
| A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision Roh, Yi-Ju; Chang, Dong-Jin; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.12, pp.2833 - 2837, 2020-12 |
| A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting Im, Jong-Pil; Wang, Se-Won; Lee, Kang-Ho; Woo, Young-Jin; Yuk, Young-Sub; Kong, Tae-Hwang; Hong, Sung-Wan; et al, 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, pp.104 - 106, IEEE, 2012-02-20 |
| A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC Seo, Min-Jae; Kim, Ye Dam; Chung, Jae-Hyun; Ryu, Seung-Tak, 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits, pp.C72 - C73, IEEE, 2019-06-11 |
| A 4th-Order Continuous-Time Delta-Sigma Modulator with Hybrid Noise-Coupling Lozada, Kent Edrian; Ryu, Seung-Tak, 65th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2022, IEEE, 2022-08-10 |
| A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization Kim, Ye-Dam; Chung, Jae-Hyun; Lozada, Kent Edrian; Chang, Dong-Jin; Ryu, Seung-Tak, 17th IEEE Asian Solid-State Circuits Conference (A-SSCC) - Integrated Circuits and Systems for the Connection of Intelligent Things, IEEE, 2021-11-07 |
| A 5.6mV Inter-Channel DVO 10b Column-Driver IC with Mismatch-Free Switched-Capacitor Interpolation for Mobile Active-Matrix LCDs Kim, Hyun-Sik; Yang, Jun-Hyeok; Park, Sang-Hui; Ryu, Seung-Tak; Cho, Gyu-Hyeong, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013, pp.392 - 393, IEEE, 2013-02-20 |
| A 54-μW fast-settling arterial pulse wave sensor for wrist watch type system Kim, Kwantae; Kim, Minseo; Cho, Hyunwoo; Lee, Kwonjoon; Ryu, Seung-Tak; Yoo, Hoi-Jun, 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, pp.1082 - 1085, Institute of Electrical and Electronics Engineers Inc., 2016-05 |
| A 550-mu W 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction Cho, Sang-Hyun; Lee, Chang-Kyo; Kwon, Jong-Kee; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.46, pp.1881 - 1892, 2011-08 |
| A 550μW 10b 40MS/s SAR ADC with multistep addition-only digital error correction Cho, S.-H.; Lee, C.-K.; Kwon, J.-K.; Ryu, Seung-Tak, 32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010, pp.561 - 564, IEEE, 2010-09-19 |
| A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration Sung, BRS; Lee, CK; Kim, W; Kim, JI; Hong, HK; Oh, GG; Lee, CH; et al, 2013 IEEE Asian Solid-State Circuits Conference, pp.281 - 284, IEEE, 2013-11-13 |
| A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS Kim, Jong-In; Sung, Ba-Ro-Saim; Kim, Wan; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.6, pp.1429 - 1441, 2013-06 |
| A 6-bit 10-GS/s 63-mW 4x TI Time-Domain Interpolating Flash ADC in 65-nm CMOS Oh, DR; Kim, JI; Seo, MJ; Kim, JG; Ryu, Seung-Tak, European Solid-State Circuits Conference, IEEE, 2015-09-17 |
| A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure Kim, Si-Nai; Kim, Wan; Lee, Chang-Kyo; Ryu, Seung-Tak, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.12, no.3, pp.270 - 277, 2012-09 |
| A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration Chang, Dong-Jin; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.3, pp.281 - 285, 2018-03 |
| A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation Kim, Jong-In; Oh, Dong-Ryeol; Jo, Dong Shin; Sung, Ba-Ro-Saim; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.10, pp.2319 - 2330, 2015-10 |
| A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration Oh, Dong-Ryeol; 김종인; Jo, Dong-Shin; Kim, Woo-Cheol; Chang, Dong-Jin; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.1, pp.288 - 297, 2019-01 |
| A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs Kim, Si-Nai; Kim, Woo Cheol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.9, pp.1154 - 1158, 2018-09 |
| A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration Kim, WooCheol; Jo, Dong Shin; Roh, Yi-Ju; Kim, Ye Dam; Ryu, Seung-Tak, 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits, pp.C138 - C139, IEEE, 2019-06-11 |
| A 6bit 1GS/s Time-interleaved Flash-SAR A/D Converter for Ultra Wide Band System Ryu, Seung-Tak; Sung, B.R.S.; Lee, Chang-Kyo; Kim, Jong-In, TriSAI 2010, 2010 |
| A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique Oh, Dong-Ryeol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2791 - 2801, 2022-09 |
| A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control Hong, Hyeok-Ki; Kim, Wan; Park, Sun-Jae; Choi, Michael; Park, Ho-Jin; Ryu, Seung-Tak, 2012 IEEE Custom Integrated Circuits Conference, IEEE, 2012-09-10 |
| A 9.1 ENOB 21.7fJ/conversion-step 10b 500MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS Moon, Kyoung-Jun; Kang, Hyun-Wook; Jo, Dong-Shin; Kim, Mi-Young; Baek, Seung-Yeob; Choi, Michael; Ko, Hyung-Jong; et al, 31st Symposium on VLSI Circuits, pp.C94 - C95, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-07 |
| A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS Moon, Kyoung-Jun; Jo, Dong-Shin; Kim, Wan; Choi, Michael; Ko, Hyung-Jong; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2532 - 2542, 2019-09 |
| A CMOS linear preamplifier design for electret microphones Park, G.-S.; Ryu, Seung-Tak, 2008 International SoC Design Conference, ISOCC 2008, v.2, IEEE, 2008-11-24 |
| A CMOS programmable gain amplifier with constant current-density based transconductance control Kang, S.Y.; Ryu, Seung-Tak; Park, Chul Soon, 2010 32nd IEEE Compound Semiconductor Integrated Circuit Symposium, CSICS 2010, pp.37 - 140, IEEE, 2010-10-03 |
| A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers Kim, Hyun-Sik; Jeon, Jin-Yong; Lee, Sung-Woo; Yang, Jun-Hyeok; Ryu, Seung-Tak; Cho, Gyu-Hyeong, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.58, no.12, pp.887 - 891, 2011-12 |
| A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC Hong, Hyeok-Ki; Kim, Wan; Kang, Hyunwook; Park, Sun-Jae; Choi, Michael; Park, Ho-Jin; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.2, pp.543 - 555, 2015-02 |
| A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs Kim, Hyeon-June; Hwang, Sun-Il; Kwon, Ji-Wook; Jin, Dong-Hwan; Choi, Byoung-Soo; Lee, Sang-Gwon; Park, Jong-Ho; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.10, pp.2262 - 2273, 2016-10 |
| A Direct Down Converted Low-Jitter Band Pass Delta Sigma Receiver with Frequency Translating Technique and Sinusoidal RF DAC So Young Kang; Dongmin Kang; Hi Yuen Song; Hyunseok Choi; Oh, Inn Yeal; Ryu, Seung-Tak; Park, Chul Soon, 2012 Asia-Pacific Microwave Conference, APMC, 2012-12-04 |
| A Dual Channel 10-b Pipelined ADC for Intelligent Transport System Ryu, Seung-Tak; Oh, Ghil-Geun, International Conference on Electron Devices and Solid-State Circuits, IEEE Electron Devices Society, 2014-06-18 |
| A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction Kim, Hyeon-June; Hwang, Sun-Il; Chung, Jaehyun; Park, Jong-Ho; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.9, pp.2488 - 2497, 2017-09 |
| A Fully Differential Rail-to-Rail Input Dynamic Latch Kim, Jong-In; Ryu, Seung-Tak, ITC-CSCC, pp.477 - 479, ITC-CSCC, 2009 |
| A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones Le, Huy-Binh; Ryu, Seung-Tak; Lee, Sang-Gug, IEICE TRANSACTIONS ON ELECTRONICS, v.E92C, pp.587 - 588, 2009-04 |
| A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels Yang, Jun-Hyeok; Park, Sang-Hui; Choi, Jung-Min; Kim, Hyun-Sik; Park, Chang-Byung; Ryu, Seung-Tak; Cho, Gyu-Hyeong, 2013 IEEE International Solid-State Circuits Conference, ISSCC 2013, pp.390 - 391, IEEE, 2013-02-20 |
| A Long Reset-Time Power-On Reset Circuit With Brown-Out Detection Capability Le, Huy-Binh; Do, Xuan-Dien; Lee, Sang-Gug; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.58, no.11, pp.778 - 782, 2011-11 |
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