A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-mu m CMOS

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This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) for bio-potential signal acquisition: skip-reset, delta (Delta) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme reduces not only reference energy but also digital switching energy for the ADC reset. The Delta-readout process with the proposed MSB-rounding technique shifts the location of the resolvable range using the previous digital code to increase the hit-rate. Finally, the tri-level split monotonic switching scheme minimizes the CDAC switching activity in predictive residue generation for the Delta-readout process. A prototype ADC was fabricated in a 0.18-mu m CMOS technology and occupies an active area of 0.17 mm(2). At a 1.5-V supply voltage and a 1-kS/s sampling-rate with the electrocardiogram signal input, the ADC power consumption could be reduced to 18.5 nW, corresponding to 71% power saving, and owing to the proposed techniques from a conventional SAR ADC consuming 63.5 nW.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-11
Language
English
Article Type
Article; Proceedings Paper
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.11, pp.3617 - 3627

ISSN
1549-8328
DOI
10.1109/TCSI.2018.2851576
URI
http://hdl.handle.net/10203/246296
Appears in Collection
EE-Journal Papers(저널논문)
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