A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

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This paper presents a CMOS image sensor (CIS) that extracts a multi-level edge image as well as a human-friendly normal image in a real time from conventional pixels for machine-vision applications, utilizing a proposed speed/power-efficient dual-mode successive-approximation register analog-to-digital converter (SAR ADC). The proposed readout scheme operates in two modes, fine step SAR (FS-SAR) mode and coarse-step single-slope (CS-SS) mode, depending on the difference (Delta) between a chosen pixel and the previous pixel. If a chosen pixel is at a boundary of an object with a large Delta from the previous pixel, the readout ADC works in the CS-SS mode to readout the edge strength (ES), while the FS-SAR mode is applied for other pixels. By displaying the ES, a multi-level edge image can be obtained in a real time along with a normal image with no hardware/time overhead. By saving the MSBs conversion cycles regardless of Delta, the proposed dual-mode readout scheme enhances the readout speed and reduces power consumption. A prototype QQVGA CIS with 10-bit SAR ADCs was fabricated in a 0.18-mu m 1P4M CMOS image sensor process with a 4.9-mu m pixel pitch. With a maximum pixel rate of 61.4 Mp/s, the prototype demonstrated figure of merits of 70 pJ/pixel/frame, 0.35 e(-) . nJ, and 0.34 e(-) . pJ/step.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2017-09
Language
English
Article Type
Article
Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.9, pp.2488 - 2497

ISSN
0018-9200
DOI
10.1109/JSSC.2017.2718665
URI
http://hdl.handle.net/10203/226130
Appears in Collection
EE-Journal Papers(저널논문)
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