A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS

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A 6-b 4.1-GS/s flash ADC was fabricated using a 90-nm CMOS with a time-domain latch interpolation technique that reduces the number of front-end dynamic comparators by half. The reduced number of comparators lowers power consumption, load capacitance to the T/H circuit, and the overhead of comparator calibration. The measured peak INL and DNL after comparator calibration are 0.74 and 0.49 LSB, respectively. The measured SNDR and SFDR are 31.2 and 38.3 dB, respectively, with a 2.02-GHz input at 4.1-GS/s operation while consuming 76 mW of total power. This ADC achieves a figure of merit of 0.625 pJ/conversion-step at 4.1 GS/s.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2013-06
Language
English
Article Type
Article
Keywords

0.35-MU-M CMOS; DIGITAL CMOS; SAR ADC; CALIBRATION; VOLTAGE

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.6, pp.1429 - 1441

ISSN
0018-9200
DOI
10.1109/JSSC.2013.2252516
URI
http://hdl.handle.net/10203/175047
Appears in Collection
EE-Journal Papers(저널논문)
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