A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs

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This paper presents a CMOS image sensor (CIS) utilizing a noise-shaping successive-approximation register analog-to-digital converter (SAR ADC) incorporating the delta-readout scheme. While the noise-shaping SAR ADC with a proposed two-tap passive finite-impulse response (FIR) filter improves effective resolution, the delta-readout scheme reduces its power consumption. A prototype 1920 x 1440 pixel CIS was fabricated in a 90-nm CIS process. A single-channel readout SAR ADC occupying an area of 22.4 mu mx 715 mu m was implemented for reading out 16 columns of pixel array, consuming 437 mu W. Owing to the proposed noise-shaping SAR ADC with oversampling ratio of 16, this paper achieves a noise reduction of 14 dB compared with the noise of a conventional SAR ADC. The delta-readout reduces the power consumption of the SAR ADC by 10% due to the high hit rate of the full high definition image format. The measured differential nonlinearity of the ADC is + 0.77/-0.54 LSB and the integral nonlinearity is + 0.81/-0.5 LSB. The prototype CIS consumes a total power of 64 mW and achieves a dynamic range of 66.5 dB and a figure of merit of 127 mu V.nJ at a data rate of 138 Mpixels/s.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-03
Language
English
Article Type
Article
Keywords

DELTA-SIGMA ADC; SNDR

Citation

IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.3, pp.1119 - 1126

ISSN
0018-9383
DOI
10.1109/TED.2018.2795005
URI
http://hdl.handle.net/10203/240924
Appears in Collection
EE-Journal Papers(저널논문)
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