Browse "College of Engineering(공과대학)" by Author Kyung, Chong-Min
Showing results 380 to 439 of 565
| N-Channel MOSFET 의 parameter 추출과 소자 simulation = Parameter extraction and device simulation on N-channel MOSFET'slink 진주현; Jin, Joo-Hyun; et al, 한국과학기술원, 1984 |
| NCPA : energy-efficient voltage scaling algorithm for multiprocessor embedded system = NCPA : 멀티프로세서 임베디드 시스템을 위한 에너지 효율적인 전압 스케일링 알고리즘link Oh, Seung-Yong; 오승용; et al, 한국과학기술원, 2008 |
| Near Optimal Scheduling in Automatic Data Path Synthesis Park, In-Cheol; Kyung, Chong-Min, Joint Technical Conference on Circuits/Systems, Computers and Communications, pp.305 - 310, 대한전자공학회, 1990 |
| NEW DESIGN RULE CHECKER BASED ON CORNER CHECKING AND BIT MAPPING Eo, K.S.; Kyung, Chong-Min, 1985 International Symposium on Circuits and Systems - Proceedings., pp.1289 - 1292, 1985 International Symposium on Circuits and Systems - Proceedings., 1985-06 |
| NEW HARDWARE ARCHITECTURE FOR FAST RASTER IMAGE GENERATION KIM, SS; EO, KS; Kyung, Chong-Min, ELECTRONICS LETTERS, v.24, no.7, pp.382 - 383, 1988-03 |
| NEW HARDWARE SCHEME SUPPORTING PRECISE EXCEPTION HANDLING FOR OUT-OF-ORDER EXECUTION HWANG, GC; Kyung, Chong-Min, ELECTRONICS LETTERS, v.30, no.1, pp.16 - 17, 1994-01 |
| New HDL for synchronus digital system and simulator implementation = 동기식 디지털 시스템을 위한 새로운 HDL의 제안 및 시뮬레이터 구현link Yang, Woo-Seung; 양우승; et al, 한국과학기술원, 1998 |
| Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods Choi, H; Kim, H; Park, In-Cheol; Hwang, Seung-Ho; Kyung, Chong-Min, Asia and South Pacific Design Automation Conference, pp.157 - 160, ASP-DAC, 1999-01 |
| Novel edge-aware cost descriptors coupled with a fast aggregation engine for efficient multi-modal depth extraction = 효율적 다중 모드 깊이 추출을 위한 고속 누적 엔진이 결합된 엣지 인지 비용 기술자link Khan, Asim; Kyung, Chong-Min; et al, 한국과학기술원, 2018 |
| Numerical Evaluation of Impurity Profile in Silicon H.C.Oh; Kyung, Chong-Min, 전기학회논문지, v.21, no.6, pp.17 - 26, 1984-11 |
| O(n)-time standard cell placement algorithm using constrained multi-stage graph model Cho, H.G.; Kyung, Chong-Min, 1988 IEEE International Symposium on Circuits and Systems, Proceedings, v.2, pp.1687 - 1690, IEEE, 1988-06 |
| Offset Aperture : A Passive Single-Lens Camera for Depth Sensing Khan, Muhammad Umar Karim; Khan, Asim; Lim, Jinyeon; Hamidov, Said; Choi, Won-Seok; Yun, Woojin; Lee, Yeongmin; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.29, no.5, pp.1380 - 1393, 2019-05 |
| OFFSET APERTURE BASED HARDWARE ARCHITECTURE FOR REAL-TIME DEPTH EXTRACTION Yun, Woojin; Kyung, Chong-Min; Kim, Young-Gyu; LEE, YEONGMIN; Lim, Jinyeon; Choi, Won-Seok; Muhammad Umar Karim, Khan; et al, 2017 IEEE International Conference on Image Processing(ICIP), pp.4392 - 4396, IEEE Signal Processing Society, 2017-09-18 |
| Opportunities and Challenges of IT Collaboration with North Korea Kyung, Chong-Min, US-Korea Conference 2007, 2007 |
| Optimal bit allocation scheme for rate-distortion control of video encoding in real-time video streaming system = 실시간 영상 스트리밍 시스템에서 비디오 인코딩의 비트 율-왜곡 제어를 위한 최적화된 비트 할당 방법link Kim, Giwon; 김기원; et al, 한국과학기술원, 2017 |
| Optimal datapath design considering deep submicron interconnects = 심층 서브마이크론 인터커넥트를 고려한 데이타 경로 최적화link Yim, Joon-Seo; 임준서; et al, 한국과학기술원, 1998 |
| OPTIMAL ENCODING OF MICROCOMMANDS IN MICROPROGRAMMED PROCESSORS Park, In-Cheol; HONG, SK; Kyung, Chong-Min, ELECTRONICS LETTERS, v.26, no.6, pp.393 - 395, 1990-03 |
| Optimal Layout Algorithm for CMOS Complex Logic Modules Kyung, Chong-Min; Kwon, Y.J., International Symposium on Circuits and Systems, 1991-06 |
| Optimistic Channel Usage between Simulator and Simulation Accelerator Kyung, Chong-Min; Lee, Jae-Gon, International SoC Design Conference(ISOCC) 2004, pp.392 - 395, 2004-10 |
| Optimized learning rate for energy waste minimization in a background subtraction based surveillance system Kyung, Chong-Min; Khan, Muhammad Umar; Yahya Khawaja M, IEEE International Symposium on Circuits and Systems(ISCAS), pp.2355 - 2360, IEEE International Symposium on Circuits and Systems(ISCAS), 2013-05-22 |
| Patch Renderer : A New Parallel Hardware Architecture for Fast Polygon Rendering Kyung, Chong-Min; S.O.Bae; G.K.Song, International Symposium on Circuits and Systems, 1991 |
| Path-based branch prediction using signature analysis Lee, S; Park, In-Cheol; Kyung, Chong-Min, MICROPROCESSORS AND MICROSYSTEMS, v.23, no.8-9, pp.527 - 536, 1999-12 |
| Path-classified trace cache for improving hit ratio in wide-issue processors Yang, JH; Park, In-Cheol; Kyung, Chong-Min, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E82D, no.10, pp.1338 - 1343, 1999-10 |
| PATH-SENSITIZED COVERING GRAPH METHOD FOR TECHNOLOGY MAPPING OF COMPLEX GATES JEONG, JC; Kyung, Chong-Min, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.74, no.10, pp.3057 - 3064, 1991-10 |
| Performance implovement of behavioral emulation system using performance model = 행위 모델 에뮬레이터의 성능 향상link Chung, Moo-Kyoung; 정무경; et al, 한국과학기술원, 2001 |
| Performance improvement of multiprocessor simulation by optimizing synchronization and communication Chung, M.-K.; Shim, H.; Kyung, Chong-Min, 16th Intetrnational Workshop on Rapid System Prototyping, RSP 2005, pp.158 - 164, RSP '05, 2005-06-08 |
| Performance maximization of 3D-stacked cache memory on DVFS-enabled processor Kang, K.; Jung, J.; Kyung, Chong-Min, 2010 International SoC Design Conference, ISOCC 2010, pp.47 - 50, 2010 International SoC Design Conference, ISOCC 2010, 2010-11-22 |
| Performance-driven design partitioning and synchronization for multi-FPGA simulation accelerator = 다중 재설정 가능 칩을 이용한 시뮬레이션 가속기의 성능 향상을 위한 디자인 분할과 동기화 알고리즘link Kwon, Young-Su; 권영수; et al, 한국과학기술원, 2004 |
| Performance-Driven Event-Based Design Mapping in Multi-FPGA Simulation Accelerator Kyung, Chong-Min; Kwon, Young-Su; Lee, Jae-Gon, International SoC Design Conference(ISOCC) 2004, pp.218 - 221, 2004-10 |
| Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus Kwon, YS; Kyung, Chong-Min, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.24, pp.1444 - 1456, 2005-09 |
| Performance-driven routing algorithm for symmetrical FPGA = 성능 최적화를 위한 대칭형 FPGA의 배선 알고리즘link Eum, Nak-Woong; 엄낙웅; et al, 한국과학기술원, 2001 |
| Performance-optimized synthesis of finite temporal property for functional coverage in co-emulation system = 에뮬레이션 시스템에서 기능검증 보장을 위해 유한한 길이의 속성을 최적화된 성능을 갖도록 합성하는 방법의 제안link Kim, Hyung-Ock; 김형옥; et al, 한국과학기술원, 2004 |
| PIPELINE ANALOG-TO-DIGITAL CONVERSION WITH CHARGE-COUPLED DEVICES. Kyung, Chong-Min; Kim, Choong Ki, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.SC-15, no.2, pp.255 - 257, 1980-04 |
| Pipeline된 부동 소수점 연산기의 설계 = A design of pipelined floating-point arithmetic unitlink 탁신제; Tak, Shin-Je; et al, 한국과학기술원, 1994 |
| Placement and global routing of arbitrarily sized rectangular functional blocks = 임의의 크기를 갖는 사격형 기능 블럭의 배치 및 전체적 배선link Choi, Hun-Kyu; 최훈규; et al, 한국과학기술원, 1986 |
| Power distribution and encoding bitrate control for event-driven surveillance Black-Box System = 사건 구동식 블랙박스 감시 시스템을 위한 전력 분배와 부호화 비트율 컨트롤 방법link Kim, Tae-Hwan; 김태환; et al, 한국과학기술원, 2011 |
| Power minimization for 2- and $3-V_{DD}$ digital circuits = 2중, 3중 전원이 공급되는 디지털 회로를 위한 전력 최소화link Ahn, Ki-Yong; 안기용; et al, 한국과학기술원, 2009 |
| Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming Kyung, Chong-Min; Ahn, Ki-Yong, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E92A, pp.2318 - 2325, 2009-09 |
| Power-Rate-Distortion Modeling for Energy Minimization of Portable Video Encoding Devices Kyung, Chong-Min; Kim, Jaemoon; Kim, Jungsoo; Kim, Giwon, The 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011-08-08 |
Practical Inter-Floor Noise Sensing System with Localization and Classification Son, Junho; Kyung, Chong-Min; Cho, Hyuntae, SENSORS, v.19, no.17, 2019-09 |
| Predictive synchronization scheme between simulator and accelerator free from performance deterioration Lee, J.-G.; Ahn, K.-Y.; Kyung, Chong-Min, 2005 International Symposium on System-on-Chip, v.2005, pp.100 - 103, 2005-11-15 |
| PrePack: Predictive packetizing scheme for reducing channel traffic in transaction-level hardware/software co-emulation Lee, Jae-Gon; Kyung, Chong-Min, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.25, no.10, pp.1935 - 1949, 2006-10 |
| PRISM : A New Strategy for Functional Block Layout Kyung, Chong-Min; Lee, P.H., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1990-12 |
| Processor energy estimation method using cycle-approximate simulator Byun, W.-H.; Kang, K.; Kyung, Chong-Min, 2008 International SoC Design Conference, ISOCC 2008, pp.288 - 291, 2008-11-24 |
| Processor energy estimation method using cycle-approximate simulator = Cycle-approximate 시뮬레이터를 사용한 프로세서 에너지 예측방법link Byun, Woo-Hong; 변우홍; et al, 한국과학기술원, 2008 |
| Profile-based Workload Prediction Method for Dynamic Voltage and Frequency Scaling in Multiprocessor Embedded System Kyung, Chong-Min; Oh, Seungyong; Kim, Jungsoo; Yoo, Sungjoo, 16th Annual IFIP International Conference On Very Large Scale Integration(IFIP-VLSI-SoC), pp.207 - 212, 2008 |
| Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling Kim, Jungsoo; Yoo, Sungjoo; Kyung, Chong-Min, 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, pp.417 - 422, 2009-04-20 |
| Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment Kim, Jungsoo; Yoo, Sungjoo; Kyung, Chong-Min, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.30, no.1, pp.110 - 123, 2011-01 |
| Pyramid texture compression and decompression using interpolative vector quantization Kwon, Y.-S.; Park, In-Cheol; Kyung, Chong-Min, International Conference on Image Processing (ICIP 2000), pp.191 - 194, IEEE, 2000-09-10 |
| PYSHA: a shadow-testing acceleration scheme for ray tracing Choi, H.K.; Kyung, Chong-Min, COMPUTER-AIDED DESIGN, v.24, no.2, pp.93 - 104, 1992-02 |
| Radix-4 multiplier with regular layout structure Park, B; Shin, M; Park, In-Cheol; Kyung, Chong-Min, ELECTRONICS LETTERS, v.34, no.15, pp.1446 - 1447, 1998-07 |
| Rate-distortion optimization-based intra encoder design = 율-왜곡 최적화 기술을 이용한 인트라 인코더 설계link Do, Jung-Ho; 도정호; et al, 한국과학기술원, 2009 |
| Ray Tracing for Moving Objects Kyung, Chong-Min; Kim, J.H., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1990-12 |
| Ray tracing using accelerated shadow testing schemes = 가속화된 그림자 검사 방식을 이용한 광선 추적link Choi, Hun-Kyu; 최훈규; et al, 한국과학기술원, 1991 |
| Reachability analysis and model checking technique for multiple-clock system verification = 다중 클락 시스템 검증을 위한 상태 도달성 분석 및 모델 확인 기술link Yi, Ju-Hwan; 이주환; et al, 한국과학기술원, 2005 |
| Real-time bundle adjustment and OPA camera depth refinement system for 3D reconstruction = 3차원 재구성을 위한 실시간 카메라 포즈/3차원 포인트 클라우드 최적화 알고리즘과 오프셋 픽셀 어퍼쳐 카메라의 깊이 맵 향상 시스템link Lim, Jinyeon; Ro, Yong Man; 노용만; Kyung, Chong-Min; et al, 한국과학기술원, 2021 |
| Real-time trace for performance analysis in OR1200 = 성능 분석을 위한 리얼타임 트레이스link Hong, Byung-Chul; 홍병철; et al, 한국과학기술원, 2008 |
| Real-traffic based simulation environment for gigabit switch chipset = 기가비트 스위치 칩셋 검증을 위한 실제 트래픽 기반의 시뮬레이션 환경link Chun, Jung-Bum; 전정범; et al, 한국과학기술원, 2000 |
| Recent Trends of Embedded Systems Design Technology Kyung, Chong-Min, US-Korea Conference 2007, 2007 |
| Rectilinear 영역에서 임의의 크기를 갖는 사각형 기능 블럭의 배치 = The placement of arbitrarily sized rectangular functional blocks within rectilinear regionlink 한효일; Han, Hyo-Il; et al, 한국과학기술원, 1989 |
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