Performance-driven design partitioning and synchronization for multi-FPGA simulation accelerator

Abstract

Simulation is the most viable solution for the functional verification of SoC. The acceleration of simulation with multi-FPGA is a promising method to comply with the increasing complexity and large gate capacity of SoC. The multi-FPGA system is characterized by the interconnection architecture to incorporate multiple FPGAs. The gate utilization of FPGAs and speed of emulation in multi-FPGA system are limited by the interconnection architecture and the number of pins. Time-multiplexing of interconnection wires is the inevitable solution to solve the pin limitation problem that limits the gate utilization of FPGAs and speed of the multi-FPGA simulation accelerator. TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) is the proposed time-multiplexed interconnection architecture for interconnecting multiple FPGAs. The most time-consuming factor of multi-FPGA simulation accelerator is the synchronization time among software simulator and multiple FPGAs. Synchronization means that intersecting signals among partitioned designs should satisfy concurrency at each simulation clock cycle. The synchronization for multi-FPGA system consists of scheduling-driven methodology and event-based methodology. This thesis proposes the circuit partitioning algorithm called SCATOMi (SCheduling-driven Algorithm for TOMi) for the inter-FPGA synchronization in multi-FPGA simulation accelerator. SCATOMi partitions the circuit for the critical path delay of the circuit to be minimized on TOMi architecture. SCATOMi improves the performance of the TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Experiments on architecture comparison show that, by adopting the proposed TOMi interconnection architecture along with SCATOMi, the pin count is reduced to 15.2%-81....