Power minimization for 2- and $3-V_{DD}$ digital circuits

Abstract

This thesis proposed an Integer Linear Programming (ILP)-based power minimization method by partitioning the target circuit into regions with two different($V_{DD})`s and with three different($V_{DD}$)s. The integer linear equation model is used to obtain optimal solution. This is to be contrasted against previous CVS solution which cannot provide optimal solution. The basic algorithm for power minimization using three-supply voltage can reduce the power consumption with 18\% compared to the case of operating with single voltage. To reduce the solving time, various technique for reducing the number of linear equations was also proposed. Applying this technique, 88\% of solving time is reduced but the difference of power consumption result is less than 0.04\%. To save the more power consumption, modified algorithm for releasing the level shifter restriction is also proposed. In this method, the power consumption with 24\% is saved compared to basic algorithm. To reduce the solving time of ILP model, node-based approach model was proposed. The solving time of integer linear equation is reduced by 90\%. The last version of proposed technique provides 29\% power saving on the average in the case of three-$V_{DD}$ compared to the case of single $V_{DD}$. Power reduction compared to Clustered Voltage Scaling(CVS) was about 18\%. To reduce the solving time of three-$V_{DD}$ case, a partitioned ILP method was proposed. Compared to the unpartitioned ILP formulation, the partitioned ILP method reduced the total solution time by 46\% at the cost of additional power consumption within 1.3\%.