New HDL for synchronus digital system and simulator implementation = 동기식 디지털 시스템을 위한 새로운 HDL의 제안 및 시뮬레이터 구현

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Most digital VLSI designs are synchronous and the two most important issues in the design are to enable fast simulation and stable synthesis. Verilog-HDL and VHDL are widely used languages for hardware description . However they have drawbacks in terms of synthesis since the synthesis is not considered when the languages were defined. Thus, in this paper we suggest a new hardware description language which is adequate for synchronous digital systems. The new HDL is defined with assuming that only hardware part to be synthesized is described using it and all other components related to simulation are modeled in C language. Since the hardware description is positioned at the middle of synthesis and simulation, we can eliminate most of the design bugs that are caused by mixed use of synthesis semantics and simulation semantics. We also developed a translation tool converting the hardware description into levelized C functions which are used to make compiled-code simulator. The customized simulator runs 2 to 7 times faster than the fastest commercial simulator.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1998
Identifier
134846/325007 / 000963356
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1998.2, [ iv, 56 p. ]

Keywords

Synchronous digital system; HDL; 하드웨어 기술 언어; 동기식 디지탈 회로; Compile-code simulation

URI
http://hdl.handle.net/10203/37063
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=134846&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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