Placement and global routing of arbitrarily sized rectangular functional blocks

Abstract

Placement and global routing of arbitrarily sized rectangular functional blocks in the chip plane are studied according to their interconnectivities. The objective of the placement is to minimize the chip area and the interconnection wire lengths. The placement process consists of three major phases: the clustering phase to analyze the block connectivities, the packing phase to deal with the size and the shape of blocks, and the trade off phase to minimize the interconnection wire lengths. In global routing, the classical shortest path algorithm is used to select the path through the routing channels to be used for interconnection net. Currently, this system runs on a MV 10000 under AOS/VS system. Tectronix 4114A or 4107 terminal is used as the graphic display, and tectronix 4631 hard copy unit is used for the final output. The entire system is implemented in C language. Many examples have been tested. For an example chip with 20 blocks and 100 pins, it takes 0.017 CPU seconds to finish the placement and the global routing.