Browse "College of Engineering(공과대학)" by Author Seo, Min-Jae
Showing results 1 to 20 of 20
| A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI- SAR) ADC Kim, Wan; Hong, Hyeok-Ki; Roh, Yi-Ju; Kang, Hyun-Wook; Hwang, Sun-Il; Jo, Dong Shin; Chang, Dong-Jin; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1826 - 1839, 2016-08 |
| A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC Chung, Jae-Hyun; Kim, Ye-Dam; Park, Chang-Un; Park, Kun-Woo; Oh, Dong-Ryeol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.59, no.8, pp.2481 - 2491, 2024-08 |
| A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section Kim, Jong Pal; Lee, Wonseok; Suh, Junyeub; Lee, Hyungwoo; Lee, Kyuil; Ahn, Ho Young; Seo, Min-Jae; et al, 42nd Annual International Conference of the IEEE-Engineering-in-Medicine-and-Biology-Society (EMBC), pp.4012 - 4015, IEEE, 2020-07 |
| A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-mu m CMOS Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Hwang, Sun-Il; Kim, Jong-Pal; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.11, pp.3617 - 3627, 2018-11 |
| A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-um CMOS Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Hwang, Sun-Il; Kim, Jong-Pal; Ryu, Seung-Tak, International Symposium on Integrated Circuits and Systems, pp.3617 - 3627, IEEE CAS Society, 2018-09-02 |
| A 2.7-M Pixels 64-mW CMOS Image Sensor With Multicolumn-Parallel Noise-Shaping SAR ADCs Hwang, Sun-Il; Chung, Jaehyun; Kim, Hyeon-June; Jang, Il Hoon; Seo, Min-Jae; Cho, Sang-Hyun; Kang, Heewon; et al, IEEE TRANSACTIONS ON ELECTRON DEVICES, v.65, no.3, pp.1119 - 1126, 2018-03 |
| A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling Jang, Il Hoon; Seo, Min-Jae; Cho, Sang-Hyun; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sunwoo; Choi, Michael; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.4, pp.1139 - 1148, 2018-04 |
| A 4.2mW 10MHz BW 74.4dB SNDR Fourth-order CT DSM with Second-order Digital Noise Coupling Utilizing an 8b SAR ADC Jang, Il-Hoon; Seo, Min-Jae; Kim, Mi-Young; Lee, Jae-Keun; Baek, Seung-Yeob; Kwon, Sun-Woo; Choi, Michael; et al, Symposium on VLSI Circuits, pp.C34 - C35, IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2017-06-06 |
| A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC Seo, Min-Jae; Kim, Ye Dam; Chung, Jae-Hyun; Ryu, Seung-Tak, 39th Symposium on VLSI Technology / 33rd Symposium on VLSI Circuits, pp.C72 - C73, IEEE, 2019-06-11 |
| A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration Chang, Dong-Jin; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.3, pp.281 - 285, 2018-03 |
| A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs Kim, Si-Nai; Kim, Woo Cheol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.9, pp.1154 - 1158, 2018-09 |
| A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique Oh, Dong-Ryeol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2791 - 2801, 2022-09 |
| A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers Jin, Dong-Hwan; Kwon, Ji-Wook; Seo, Min-Jae; Kim, Mi-Young; Shin, Min-Chul; Kang, Seok-Joon; Yoon, Jung-Hyuk; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.6, pp.1812 - 1823, 2019-06 |
| A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks Seo, Min-Jae; Roh, Yi-Ju; Chang, Dong-Jin; Kim, Wan; Kim, Ye-Dam; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.12, pp.1904 - 1908, 2018-12 |
| A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye Dam; Kim, Jong-Pal; Chang, Dong-Jin; Lim, Won-Mook; Chung, Jaehyun; et al, 15th IEEE Asian Solid-State Circuits Conference, A-SSCC 2019, pp.189 - 192, Institute of Electrical and Electronics Engineers Inc., 2019-11 |
| A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Kim, Jong-Pal; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.55, no.10, pp.2660 - 2669, 2020-10 |
| An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd-Order Noise-Shaping Interpolating SAR ADC Chung, Jaehyun; Kim, Ye Dam; Park, Chang Un; Park, Kunwoo; Seo, Min-Jae; Ryu, Seung-Tak, 44th Annual IEEE Custom Integrated Circuits Conference, CICC 2023, IEEE, 2023-04-25 |
| High resolution & low noise SAR ADC design for bio-medical signal acquisition = 생체 신호 획득을 위한 고해상도 및 저전력 축차 비교형 아날로그-디지털 변환기 설계link Seo, Min-Jae; Ryu, Seung-Tak; et al, 한국과학기술원, 2019 |
| Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC Chang, Dong-Jin; Kim, Wan; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.2, pp.322 - 332, 2017-02 |
| 비교축차형 아날로그-디지털 변환기의 설계 자동화 연구 = Study on design automation of successive approximation register ADClink 서민재; 류승탁; et al, 한국과학기술원, 2015 |
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