Browse "School of Electrical Engineering(전기및전자공학부)" by Author Hwang, Chanwoong
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| 32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk, 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp.442 - 444, IEEE, 2021-02-13 |
| A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC Park, Suneui; Kim, Juyeop; Hwang, Chanwoong; Park, Hangi; Yoo, Seyeon; Seong, Taeho; Choi, Jaehyouk, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.29, no.8, pp.548 - 550, 2019-08 |
| A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Hwang, Chanwoong; Park, Hangi; Seong, Taeho; Choi, Jaehyouk, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.378 - 380, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M Hwang, Chanwoong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2841 - 2855, 2022-09 |
| A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.12, pp.3527 - 3537, 2022-12 |
| A-58dBc-Worst-Fractional-Spur and-234dB-FoM(jitter), 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word Seong, Taeho; Lee, Yongsun; Hwang, Chanwoong; Lee, Jeonghyun; Park, Hangi; Lee, Kyuho Jason; Choi, Jaehyouk, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.270 - 272, Institute of Electrical and Electronics Engineers Inc., 2020-02-19 |
| An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS Yoo, Seyeon; Park, Suneui; Choi, Seojin; Cho, Yoonseo; Yoon, Heein; Hwang, Chanwoong; Choi, Jaehyouk, 2021 IEEE International Solid- State Circuits Conference (ISSCC), IEEE, 2021-02-13 |
| INTEGRATED CIRCUIT, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF Choi, Jaehyouk; Seong, Taeho; Lee, Yongsun; Hwang, Chanwoong; Park , Hangi |
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