A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector

Abstract

Modern SoCs for advanced wireless/wired applications integrate an increasing number of PLLs. 5G TRXs require multiple PLLs to implement complex schemes of carrier aggregation and MIMO. Multilane high-speed serial links for high data throughput also require many PLLs. To maximize the area efficiency, ring-oscillator (RO)-based digital PLLs (DPLLs) are the obvious alternative to the conventional LC-oscillator analog PLLs (LC-PLLs). To overcome the well-known problem of the high jitter of an RO, the general design guideline is to extend the loop bandwidth. However, this strategy cannot be applied readily to a fractional-N architecture, since a wide bandwidth cannot prevent various in-band noise sources from degrading the overall jitter. Recently, many techniques have been presented to suppress those noise sources. The optimal-threshold TDC (OT TDC) [1] and the noise-shaping BBPD [2] are efficient techniques to reduce the quantization noise (Q-noise) of the TDC. The use of DTCs to cancel the Q-noise of the M has now become a general solution. To suppress the detrimental effects of the DTC nonlinearity, such as M Q-noise leakage, fractional spurs, and noise folding, linearization techniques also have been presented. Modulating the statistical property of the M code (e.g., probability-density-shaping (PDS)-M [3]) is another approach to avoid fractional spurs due to the DTC nonlinearity. Recently, the fractional-N RO DPLL in [3] (at the top left of Fig. 23.2.1) achieved the rms jitter of less than 400fs by extending the loop bandwidth in addition to using the various techniques described above to reduce in-band noise. However, this level of rms jitter is still much higher than that of advanced LC-PLLs. The graph of the in-band noise sources at the top right of Fig. 23.2.1 shows that, to further decrease the rms jitter, the next challenge is to reduce the thermal noise of the DTC, which increases in proportion to its required range [4]. Spending more power on the DTC might be an easy solution, but it degrades the overall FoMjitter of the DPLL. Thus, more advanced and efficient solutions are needed.