Browse "School of Electrical Engineering(전기및전자공학부)" by Subject offset calibration
Showing results 1 to 6 of 6
| A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source Kim, Young-Hwa; Cho, SeongHwan, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.7, pp.2570 - 2579, 2016-07 |
| A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS Kim, Jong-In; Sung, Ba-Ro-Saim; Kim, Wan; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.6, pp.1429 - 1441, 2013-06 |
| A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration Oh, Dong-Ryeol; 김종인; Jo, Dong-Shin; Kim, Woo-Cheol; Chang, Dong-Jin; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.1, pp.288 - 297, 2019-01 |
| A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique Oh, Dong-Ryeol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2791 - 2801, 2022-09 |
| An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS Oh, Dong-Ryeol; Moon, Kyoung-Jun; Lim, Won-Mook; Kim, Ye-Dam; An, Eun-Ji; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.4, pp.1216 - 1226, 2021-04 |
| Latch interpolation technique for high-speed flash ADC = 고속 플래시 아날로그/디지털 변환기를 위한 래치 인터폴레이션 기법link Kim, Jongin; 김종인; et al, 한국과학기술원, 2015 |
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