A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source

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A zero-crossing-based circuit (ZCBC) is a promising technique for low-power high-resolution pipeline analog-to-digital converters (ADCs). Unfortunately, operating ZCBC ADCs at high speeds near 1 GS/s is quite challenging due to the delay of the zero-crossing detector that introduces nonlinear gain and offset errors. To solve nonlinearity, we propose a ZCBC pipeline ADC that employs a passive resistor as a current source. Due to its inherent linearity, the resistor-based ZCBC eliminates the input dependency of the interstage gain and offset errors, allowing a simple calibration. Furthermore, a background offset calibration scheme is proposed to cope with the large offset that results from high-speed operation. A prototype ADC implemented in 65-nm CMOS achieves an SNDR/SFDR of 47.26/62.64 dB at 1 GS/s while consuming 46.52 mW from 1 V supply
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-07
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.7, pp.2570 - 2579

ISSN
1063-8210
DOI
10.1109/TVLSI.2015.2508564
URI
http://hdl.handle.net/10203/212871
Appears in Collection
EE-Journal Papers(저널논문)
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