Browse "School of Electrical Engineering(전기및전자공학부)" by Author Park, Hangi
Showing results 1 to 11 of 11
| 32.1 A 365fsrms-Jitter and -63dBc-Fractional Spur 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC Second/Third- Order Nonlinearity Cancelation and a Probability-Density-Shaping ΔΣM Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Lee, Yongsun; Choi, Jaehyouk, 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp.442 - 444, IEEE, 2021-02-13 |
| 32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique Kim, Juyeop; Jo, Yongwoo; Lim, Younghyun; Seong, Taeho; Park, Hangi; Yoo, Seyeon; Lee, Yongsun; et al, 2021 IEEE International Solid- State Circuits Conference (ISSCC), pp.448 - 450, IEEE, 2021-02-13 |
| A -240dB-FoMjitter and -115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction Lee, Yongsun; Seong, Taeho; Lee, Jeonghyun; Hwanq, Chanwoong; Park, Hangi; Choi, Jaehyouk, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.266 - 268, Institute of Electrical and Electronics Engineers Inc., 2020-02-19 |
| A 0.1-1.5-GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC Park, Suneui; Kim, Juyeop; Hwang, Chanwoong; Park, Hangi; Yoo, Seyeon; Seong, Taeho; Choi, Jaehyouk, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.29, no.8, pp.548 - 550, 2019-08 |
| A 170MHz-Lock-In-Range and-253dB-FoM(jitter), 12-to-14.5GHz Subsampling PLL with a 150 mu W Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Yoo, Seyeon; Park, Hangi; Yoon, Heein; et al, IEEE International Solid-State Circuits Conference (ISSCC), pp.280 - 282, IEEE, 2020-02-19 |
| A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Hwang, Chanwoong; Park, Hangi; Seong, Taeho; Choi, Jaehyouk, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.378 - 380, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
| A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping Delta sigma M Hwang, Chanwoong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2841 - 2855, 2022-09 |
| A Low-jitter Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction Hwang, Chan woong; Park, Hangi; Lee, Yongsun; Seong, Taeho; Choi, Jaehyouk, IDEC Journal of Integrated Circuits and Systems, v.9, no.4, pp.37 - 43, 2023-10 |
| A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Park, Hangi; Hwang, Chanwoong; Seong, Taeho; Choi, Jaehyouk, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.12, pp.3527 - 3537, 2022-12 |
| A-58dBc-Worst-Fractional-Spur and-234dB-FoM(jitter), 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word Seong, Taeho; Lee, Yongsun; Hwang, Chanwoong; Lee, Jeonghyun; Park, Hangi; Lee, Kyuho Jason; Choi, Jaehyouk, 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.270 - 272, Institute of Electrical and Electronics Engineers Inc., 2020-02-19 |
| An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators Kim, Juyeop; Lim, Younghyun; Yoon, Heein; Lee, Yongsun; Park, Hangi; Cho, Yoonseo; Seong, Taeho; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.12, pp.3466 - 3477, 2019-12 |
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