Browse "School of Electrical Engineering(전기및전자공학부)" by Author Park, CS

Showing results 1 to 20 of 20

1
A novel approach for integration of dual metal gate process using ultra thin aluminum nitride buffer layer

Cho, Byung Jin; Park, CS; N. Balasubramanian, N; Kwong, DL, Symposium on VLSI Technology, pp.149 - 149, 2003-06-10

2
A robust stereo disparity estimation using adaptive window search and dynamic programming search

Park, CS; Park, HyunWook, PATTERN RECOGNITION, v.34, no.12, pp.2573 - 2576, 2001-12

3
An integratable dual metal gate CMOS process using an ultrathin aluminum nitride buffer layer

Park, CS; Cho, Byung Jin; Kwong, DL, IEEE ELECTRON DEVICE LETTERS, v.24, no.5, pp.298 - 300, 2003-05

4
Demonstration of Low Vt NMOSFETs Using Thin HfLaO in ALD TiN/HfSiO Gate Stack

Cho, Byung Jin; Park, CS; Song, SC; Bersuker, G; Alshareef, HN; Ju, BS; Majhi, 2006 International Conference on Solid State Devices and Materials (SSDM 2006), pp.0 - 0, 2006-09-12

5
Dopant-free FUSI PtxSi metal gate for high work function and reduced Fermi-level pinning

Park, CS; Cho, Byung Jin, IEEE ELECTRON DEVICE LETTERS, v.26, no.11, pp.796 - 798, 2005-11

6
Doped fibre length and pump power of gain-flattened EDFAs

Park, SY; Kim, HK; Park, CS; Shin, Sang Yung, ELECTRONICS LETTERS, v.32, no.23, pp.2161 - 2162, 1996-11

7
Dual Metal Gate Process by Metal Substitution of Dopant-Free Polysilicon on High-K Dielectric

Cho, Byung Jin; Park, CS; Hwang, WS; Loh, WY; Tang, LJ; Kwong, DL, Symposium on VLSI Technology, pp.48 - 49, 2005-06-14

8
Dual metal gate process scheme for wide range work function modulation and reduced Fermi level pinning

Cho, Byung Jin; Park, CS; Lwin, PW; Wong, SY; Pu, J; Hwang, WS, 3rd International Conference on Materials for Advanced Technologies, pp.41 - 41, 2005-07-03

9
Feasibility study of using thin aluminum nitride film as a buffer layer for dual metal gate process

Park, CS; Cho, Byung Jin; Balasubramanian, N; Kwong, DL, THIN SOLID FILMS, v.462, pp.15 - 18, 2004-09

10
Interface configuration and Fermi-level pinning of fully silicided gate and high-K dielectric stack

Joo, MS; Park, CS; Cho, Byung Jin; Balasubramanian, N; Kwong, DL, JOURNAL OF VACUUM SCIENCE TECHNOLOGY B, v.24, no.3, pp.1341 - 1343, 2006-05

11
MOS characteristics of substituted Al gate on high-kappa dielectric

Park, CS; Cho, Byung Jin; Kwong, DL, IEEE ELECTRON DEVICE LETTERS, v.25, no.11, pp.725 - 727, 2004-11

12
MOS characteristics of synthesized HfAlON-HfO2 stack using AIN-HfO2

Park, CS; Cho, Byung Jin; Kwong, DL, IEEE ELECTRON DEVICE LETTERS, v.25, no.9, pp.619 - 621, 2004-09

13
Novel mode converter based on hollow optical fiber for gigabit LAN communication

Choi, S; Oh, K; Shin, W; Park, CS; Paek, UC; Park, KJ; Chung, Yun Chur; et al, IEEE PHOTONICS TECHNOLOGY LETTERS, v.14, no.2, pp.248 - 250, 2002-02

14
Omnidirectional Robot System and Localization for FIRA ROBOSOT

Kim, Jong-Hwan; Lee, DH; Sun, JS; Han, SB; Park, CS, FIRA Robot World Congress, Qingdao, 2008

15
Phase development of radio-frequency magnetron sputter-deposited Pb(Mg1/3Nb2/3)O-3-PbTiO3 (90/10) thin films

Lee, JK; Park, D; Cheong, DS; Park, JW; Park, CS, JOURNAL OF VACUUM SCIENCE TECHNOLOGY A-VACUUM SURFACES AND FILMS, v.18, no.4, pp.1659 - 1662, 2000-04

16
Substituted Aluminum Metal Gate on high-K Dielectric for low work-function and Fermi-Level Pinning Free

Cho, Byung Jin; Park, CS; Tang, LJ; Kwong, DL, International Electron Device Meeting (IEDM), pp.0 - 0, 2004-12-13

17
The effect of Ge composition and Si cap thickness on hot carrier reliability of Si/Si1-xGex/Si p-MOSFETs with high-K/metal gate

Cho, Byung Jin; Loh, WY; Majhi, P; Lee, SH; Oh, JW; Sassman, B; Young, C; et al, 2008 Symposium on VLSI Technology, pp.56 - 57, 2008-06-17

18
Thermally stable fully silicided Hf-silicide metal-gate electrode

Park, CS; Cho, Byung Jin; Kwong, DL, IEEE ELECTRON DEVICE LETTERS, v.25, no.6, pp.372 - 374, 2004-06

19
Top-Surface Aluminized and Nitrided Hafnium Oxide Using Synthesis of Thin AlN and HfO2 Stacked Layer

Cho, Byung Jin; Park, CS; Tang, LJ; Wang, W; Kwong, DL, Conf. on Solid State Devices and Materials (SSDM), pp.0 - 0, 2004-09-14

20
Trans-impedance amplifier of source follower topology using an active device for bandwidth extension in optical communication systems

Jung, D.Y.; Ji, H.G.; Kim, H.C.; Nam, E.S.; Park, CS, JOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.45, no.3, pp.761 - 764, 2004-09

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