Browse "School of Electrical Engineering(전기및전자공학부)" by Title
Showing results 35881 to 35900 of 51102
| Synthesis of application specific instructions for embedded DSP software = 내장형 DSP 소프트웨어를 위한 응용분야 전용 명령어의 생성link Choi, Hoon; 최훈; et al, 한국과학기술원, 1999 |
| Synthesis of application specific instructions for embedded DSP software Choi, H; Park, In-Cheol; Hwang, SH; Kyung, Chong-Min, Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, ICCAD, pp.665 - 671, IEEE, 1998-11-08 |
| Synthesis of application-specific coprocessor for core-based ASIC design Lee, DH; Park, In-Cheol; Kyung, Chong-Min, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E84A, no.2, pp.604 - 613, 2001-02 |
| Synthesis of application-specific coprocessors for core-based ASIC design = 코어 기반의 ASIC 설계를 위한 응용 분야 전용 코프로세서의 합성link Lee, Dae-Hyun; 이대현; et al, 한국과학기술원, 2001 |
| Synthesis of brain tumor MR images for learning data augmentation = 학습 데이터 증강을 위한 뇌 종양 자기 공명 영상 합성link Kim, Sunho; Park, HyunWook; et al, 한국과학기술원, 2020 |
| Synthesis of brain tumor multicontrast MR images for improved data augmentation Kim, Sunho; Kim, Byungjai; Park, HyunWook, MEDICAL PHYSICS, v.48, no.5, pp.2185 - 2198, 2021-05 |
| Synthesis of Clock Gating Logic through Factored Form Matching Han, Inhak; Shin, Youngsoo, IEEE International Conference on Integrated Circuit Design and Technology, IEEE, 2012-05-31 |
| Synthesis of corrugated waveguide filters by the gel'fand-levitan-marchenko inverse scattering method = 역산란방법에 의한 격자필터의 설계link Sohng, Ghie-Hugh; 송계휴; et al, 한국과학기술원, 1982 |
| Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization Kim, Sangmin; Kang, Seokhyeong; Shin, Youngsoo, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.21, no.3, 2016-07 |
| Synthesis of dual-mode circuits through optimizing transition time constraints Kim, Sang-Min; Chang, Ik Joon; Shin, Youngsoo, International Conference on Consumer Electronics, IEEE, 2016-10-26 |
| Synthesis of Epitaxial Graphene using Pulsed Laser Annealing Choi, Insung; Choi, Sung-Yool; Lee, Keonjae, ENGE 2012, ENGE 2012, 2012-09-17 |
| Synthesis of fault-tolerant supervisor for automated manufacturing systems: A case study on photolithographic process Cho, Kwang-Hyun; Lim, Jong-Tae, IEEE TRANSACTIONS ON ROBOTICS AND AUTOMATION, v.14, no.2, pp.348 - 351, 1998-04 |
| Synthesis of flat-top bandpass filters using two-band rejection long-period fiber gratings Kim, HK; Bae, JH; Chun, Joohwan, IEEE PHOTONICS TECHNOLOGY LETTERS, v.19, no.17-20, pp.1466 - 1468, 2007-09 |
| Synthesis of freestanding cupric oxide nanotubes with close ends from copper nanowires by the Kirkendall effect Park, Sungho; Chae, Wonseok; Han, Manso; Jeon, Sanghun, JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, v.34, no.5, 2016-09 |
| Synthesis of Graphene - MoS2 Lateral Heterostructure and its FET Application Hong, Woonggi; Shim, Gi Woong; Yang, Sang Yoon; Jung, Dae Yool; Choi, Sung-Yool, NANO KOREA 2017, NANO KOREA 2017, 2017-07-13 |
| Synthesis of graphene for electronic device and system applications 조병진, 2013년 한국탄소학회 추계학술대회, Korean Carbon Society, 2013-11-18 |
| Synthesis of graphene layers by inductive coupled plasma enhanced chemical vapor deposition (ICP-CVD) for application in optoelectronics Thant, Aye Aye; Jung, Dae-Yool; Lee, Jung-Yong; Choi, Sung-Yool, Photonics for Energy, PFE_2019, OSA - The Optical Society, 2019-11 |
| Synthesis of large-scale graphene layers on metal thin films and application to electronic devices Cho, Byung Jin; Mun, Jeong Hun; Song, Seung Min; Noh, Young Dal; Kang, Byung Jin, International Conference on Electronic Materials 2010, International Union of Materials Research Societies, 2010-08 |
| Synthesis of lithographic test patterns through topology-oriented pattern extraction and classification Shim, Seongbo; CHUNG, WOOHYUN; Shin, Youngsoo, SPIE Advanced Lithography, pp.1 - 10, SPIE, 2014-02-25 |
| Synthesis of Lithography Test Patterns Using Machine Learning Model Kareem, Pervaiz; Shin, Youngsoo, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.34, no.1, pp.49 - 57, 2021-02 |
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