Synthesis of application-specific coprocessors for core-based ASIC design

Abstract

As electronic systems require high performance and the design complexity rapidly increases, the core-based ASIC design approach becomes more and more popular these days. A core-based ASIC is actually a mixture of hardware and software: one or more dedicated hardware units - application-specific coprocessors - to implement the hardware part and a set of software routines running on a dedicated processor core. Most of hardware/software codesign approaches for core-based ASIC design have been focusing on how to partition the given specification into hardware and software at the high-level. Their common drawbacks are 1) they ignore that there exist a lot of candidates with different performance metric in implementing coprocessors, 2) they don``t consider the cycle-time requirement on synthesized coprocessors. In addition, few approaches handle the problem of power consumption, which is one of the most important metric in modern electronics systems. As the design constraints become tighter, we need to consider above problems for practical reasons. Therefore, in this thesis, we propose three approaches for core-based ASIC design that carefully investigate above three factors. The first approach synthesizes a coprocessor under time constraint. We formulate both the mapping of DFGs to hardware or software and the selection of the appropriate hardware implementation for each DFG as a single integer programming problem, and then apply an iterative algorithm based on the Kernighan and Lin`s heuristic to solve the problem. To reduce the CPU time, we have devised data structures that quickly calculate costs of hardware implementations. Experimental results demonstrate that our approach outperforms the previous approach based on genetic algorithm in both the coprocessor area and the CPU time. The second approach synthesizes a coprocessor under not only the time constraint but also the cycle-time constraint. We model the coprocessor from the first approach as a timing grap...