Browse by Subject TSV
Showing results 1 to 26 of 26
| 3 Dimensional transmission line matrix (3D TLM) modeling and analysis of through silicon via (TSV) coupling in 3 dimensional integrated circuit (3D IC) = 3차원 전송선 매트릭스 방법을 이용한 3차원 집적회로에서 사용되는 실리콘 관통 비아의 잡음전달 현상에 대한 모델링 및 분석link Cho, Jong-Hyun; 조종현; et al, 한국과학기술원, 2010 |
| 30 Gbps High-Speed Characterization and Channel Performance of Coaxial Through Silicon Via Jung, Daniel Hyunsuk; Kim, Hee-Gon; Kim, Suk Jin; Kim, Jonghoon J.; Bae, Bumhee; Kim, Jonghoon; Yook, Jong-Min; et al, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.24, no.11, pp.814 - 816, 2014-11 |
| 3차원 적층 패키지용 인터커넥션 공정에 관한 연구 = A study on interconnection process of 3D packaginglink 김선락; Kim, Sun-Rak; et al, 한국과학기술원, 2013 |
| A study on the interconnection properties of 3D TSV chip using non-conductive films(NCFs) with thermal acid generator(TAG) = 산 발생제를 함유한 비전도성 접합필름(NCF)을 이용한 관통비아 칩의 접속특성에 대한 연구link Choi, Yong-Won; 최용원; et al, 한국과학기술원, 2014 |
| (A) Fault-tolerant scheme for TSV-based 3D network-on-chip = TSV기반 3D 네트워크-온-칩을 위한 결함-허용 기법link Lee, Jae-Young; 이재영; et al, 한국과학기술원, 2013 |
| (A) study on Non-Conductive Film (NCF) materials and bonding conditions for high-speed Cu Pillar/Sn-Ag hybrid-bump bonding = 구리 필라/주석-은 하이브리드 범프의 고속 본딩을 위한 비전도성 필름과 본딩 조건에 대한 연구link Yu, Young Hyun; Paik, Kyoung Wook; et al, 한국과학기술원, 2017 |
| An Improved 100 GHz Equivalent Circuit Model of a Through Silicon Via With Substrate Current Loop Kim, Kibeom; Hwang, Karam; Ahn, Seungyoung, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.26, no.6, pp.425 - 427, 2016-06 |
| Analysis of 3D TSV Vertical Interconnection Using Pre-applied Nonconductive Films Choi, Yong-Won; Shin, Ji Won; Suk, Kyung-lim; Kim, Youngsoon; Kim, Il; Paik, Kyung-Wook, JOURNAL OF ELECTRONIC MATERIALS, v.43, no.11, pp.4214 - 4223, 2014-11 |
| BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems Wang, Chao; Zhou, Jun; Weerasekera, Roshan; Zhao, Bin; Liu, Xin; Royannez, Philippe; Je, Minkyu, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.62, no.1, pp.139 - 148, 2015-01 |
| Effect of Process Parameters on TSV Formation Using Deep Reactive Ion Etching Kim, Kwang-Seok; Lee, Young-Chul; Ahn, Jee-Hyuk; Song, Jun Yeob; Yoo, Choong D.; Jung, Seung-Boo, KOREAN JOURNAL OF METALS AND MATERIALS, v.48, no.11, pp.1028 - 1034, 2010-11 |
| Filling of very fine via holes for 3D packaging by using ionized metal plasma sputtering and electroplating CHO, Byeong-Hoon; YUN, Jae-Jin; LEE, Won-Jong, Japanese Journal of Applied Physics, Vol.46, No.46, pp.L1135-L1137, 2007-11-22 |
| Filling of very fine via holes for three-dimensional packaging by using ionized metal plasma sputtering and electroplating Cho, Byeong-Hoon; Yun, Jae-Jin; Lee, Won-Jong, JAPANESE JOURNAL OF APPLIED PHYSICS, v.46, no.45-49, pp.L1135 - L1137, 2007-12 |
| High-Frequency Modeling and Signal Integrity Analysis of a Silicone Rubber Socket for High-Performance Package Kim, Hyesoo; Kim, Jonghoon J.; Park, Junyong; Park, Shinyoung; Choi, Sumin; Bae, Bumhee; Ha, DongHo; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.7, no.8, pp.1356 - 1368, 2017-08 |
| High-Frequency Scalable Modeling and Analysis of a Differential Signal Through-Silicon Via Kim, Joo-Hee; Cho, Jong-Hyun; Kim, Joungho; Yook, Jong-Min; Kim, Jun Chul; Lee, Junho; Park, Kunwoo; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.4, no.4, pp.697 - 707, 2014-04 |
| Modeling and analysis of LC-VCO performance degradation and shielding for tsv noise coupling in 3D IC = 3차원 집적회로에서 실리콘 관통 비아의 잡음전달과 LC-VCO 성능 저하의 모델링 및 분석과 차폐에 대한 연구link Lim, Jae-Min; 임재민; et al, 한국과학기술원, 2014 |
| Modeling and analysis of noise coupling and RF sensitivity in through-silicon-via (TSV) silicon interposer = 실리콘 관통 비아 실리콘 인터포져에서의 노이즈 커플링 모델링과 RF감도 해석link Yoon, Ki-Hyun; 윤기현; et al, 한국과학기술원, 2010 |
| Modeling and analysis of power distribution network in 2.5D and 3D IC based on segmentation method and target impedance considering current spectrum = 구조분할 방법과 전류 스펙트럼에 기반한 목표 임피던스를 이용한 2.5차원/3차원 반도체에서 전력분배망의 모델링 및 분석link Kim, Youngwoo; 김영우; et al, 한국과학기술원, 2015 |
| More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs Song, Taigon; Panth, Shreepad; Chae, Yoo-Jin; Lim, Sung Kyu, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.35, no.12, pp.2056 - 2067, 2016-12 |
| Non-conductive film with Zn-nanoparticles (Zn-NCF) for 40 mu m pitch Cu-pillar/Sn-Ag bump interconnection Shin, Ji Won; Kim, Il; Choi, Yong-Won; Kim, Youngsoon; Kang, Un Byung; Jee, Young Kun; Paik, Kyung-Wook, MICROELECTRONICS RELIABILITY, v.55, no.2, pp.432 - 441, 2015-02 |
| Non-destructive micro-Raman analysis of Si near Cu through silicon via Kim, Jae Hyun; Yoo, Woo Sik; Han, Seung Min, ELECTRONIC MATERIALS LETTERS, v.13, no.2, pp.120 - 128, 2017-03 |
| Rigorous mathematical model of through-silicon via capacitance Kim, Kibeom; Kim, Jedok; Kim, Hongkyun; Ahn, Seungyoung, IET CIRCUITS DEVICES & SYSTEMS, v.12, no.5, pp.589 - 593, 2018-09 |
| Temperature-dependent through-silicon via (TSV) model and isolation characteristics = 온도에 의존하는 관통 실리콘 비아 모델과 아이솔레이션 특성link Lee, Man-Ho; 이만호; et al, 한국과학기술원, 2012 |
| Through-Silicon Via Capacitance-Voltage Hysteresis Modeling for 2.5-D and 3-D IC Kim, Dong-Hyun; Kim, Youngwoo; Cho, Jong-Hyun; Bae, Bumhee; Park, Junyong; Lee, Hyunsuk; Lim, Jaemin; et al, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.7, no.6, pp.925 - 935, 2017-06 |
| Through-Silicon-Via-Based Decoupling Capacitor Stacked Chip in 3-D-ICs Song, Eun-Seok; Koo, Kyoung-Choul; Pak, Jun-So; Kim, Joung-Ho, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.3, no.9, pp.1467 - 1480, 2013-09 |
| Vertical Noise Coupling From On-Chip Switching-Mode Power Supply in a Mixed-Signal Stacked 3-D-IC Koo, Kyoung-Choul; Kim, Myung-Hoi; Kim, Jonghoon J.; Kim, Joung-Ho; Kim, Ji-Seong, IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, v.3, no.3, pp.476 - 488, 2013-03 |
| 수직성장시킨 CNT와 금속의 복합재료를 이용한 through-Si via/trench filling에 관한 연구 = Study on the through-Si via/trench filling with vertically-grown CNT and metal compositelink 최승욱; Choi, Seung-Wook; et al, 한국과학기술원, 2010 |
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