In recent years, 3-dimensional integration circuits (3D ICs) technology with Through-Silicon Via (TSV) has become a new paradigm in semiconductor industry. A TSV provides reduced interconnection in a vertical direction so that may reduce the time delay of signals. Also, this shortest electrical path between stacked chips allows low power packaging scheme compared to conventional wire bonding and flip chip technologies. In spite of these advantages, there exist some issues that should be overcome. First, signal integrity issues exist such as noise coupling result from the silicon substrate between TSVs or TSV channel transmission characteristic varia-tion. Noise coupling between signal TSVs can increase jitter, phase noise or the clock signal, and power ground noise. Second, stacked dies have possibility to isolate themselves from heat dissipation. This thermal issue should be carefully investigated.
Most of signal integrity researches do not consider actual temperature range, but they mostly assume room temperature situation where every material of TSV-based structure has fixed electrical properties as tem-perature varies. The thermal issue in 3D ICs is very important from the view point of fundamental level of manufacturing, but the effect of the temperature rising can cause problems directly related to signal issues as well. Thus, temperature dependence analysis of TSV in 3D ICs should be investigated.
The effect of temperature variation from 25°C to 100°C on TSV noise coupling and channel transmission characteristic S21 magnitude are measured in this paper; this temperature range is generally chosen for proper chip operation. The temperature was increased with the heat convection method to minimize the electrical effect and the approximated temperature profile was obtained using a thermal imaging camera. The measurement result was analyzed with temperature-dependent TSV lumped model and showed good correlation.
In addition, TSV has basically MOS structure,...