Reducing non-deterministic loads in low-power caches via early cache set resolution

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Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of non-determinism in cache access latency. Due to this additional latency, instructions dependent on a load speculatively issued must be squashed and re-issued as they will not have the correct data in time. Our experiments show that there is a large performance degradation and associated dynamic energy wastage due to these effects of instruction squashing. To address this problem, we propose an early cache set resolution scheme. Our experimental evaluation shows that this technique is quite effective in mitigating the problem. (c) 2006 Elsevier B.V. All rights reserved.
Publisher
ELSEVIER SCIENCE BV
Issue Date
2007-08
Language
English
Article Type
Article
Keywords

MICROPROCESSOR; PERFORMANCE; ENERGY

Citation

MICROPROCESSORS AND MICROSYSTEMS, v.31, no.5, pp.293 - 301

ISSN
0141-9331
DOI
10.1016/j.micpro.2006.10.002
URI
http://hdl.handle.net/10203/89672
Appears in Collection
CS-Journal Papers(저널논문)
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