Researcher Page

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Kim, Soontae (김순태)
부교수, School of Computing(전산학부)
Research Area
Embedded Computing, Computer Architecture, Low­Power, Reliability, Real­Time
Co-researchers
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    NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
    1
    CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems

    Kim, Jinkwon; Hong, Seokin; Hong, Jeongkyu; et al, IEEE TRANSACTIONS ON COMPUTERS, v.70, no.7, pp.1132 - 1145, 2021-07

    2
    An L2 Cache Architecture Supporting Bypassing for Low Energy and High Performance

    Park, Jungwoo; Kim, Soontaeresearcher; Hou, Jong-Uk, ELECTRONICS, v.10, no.11, 2021-06

    3
    ECC-United Cache: Maximizing Efficiency of Error Detection/Correction Codes in Associative Cache Memories

    Farbeh, Hamed; Delshadtehrani, Leila; Kim, Hyeonggyu; et al, IEEE TRANSACTIONS ON COMPUTERS, v.70, no.4, pp.640 - 654, 2021-04

    4
    SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches

    Qureshi, Muhammad Avais; Park, Jungwoo; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.6, pp.1357 - 1370, 2020-06

    5
    Freezing: Eliminating Unnecessary Drawing Computation for Low Power

    Seo, Bohun; Kim, Hyeonggyu; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.39, no.1, pp.56 - 61, 2020-01

    6
    Time-sensitivity-aware shared cache architecture for multi-core embedded systems

    Lee, Myoungjun; Kim, Soontaeresearcher, JOURNAL OF SUPERCOMPUTING, v.75, no.10, pp.6746 - 6776, 2019-10

    7
    Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages

    Lee, Wonyoung; Kang, Mincheol; Hong, Seokin; et al, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.9, pp.2033 - 2045, 2019-09

    8
    MH Cache: A Multi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems

    Park, Jungwoo; Lee, Myoungjun; Kim, Soontaeresearcher; et al, ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, v.16, no.3, 2019-08

    9
    Restore-Free Mode for MLC STT-RAM Caches

    Qureshi, Muhammad Avais; Kim, Hyeonggyu; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.27, no.6, pp.1465 - 1469, 2019-06

    10
    소형 무인 항공기 탐지를 위한 인공 신경망 기반 FMCW 레이다 시스템

    장명재; 김순태researcher, 대한임베디드공학회논문지, v.13, no.6, pp.289 - 296, 2018-12

    11
    Subpage-Aware Solid State Drive for Improving Lifetime and Performance

    Kang, Mincheol; Lee, Wonyoung; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON COMPUTERS, v.67, no.10, pp.1492 - 1505, 2018-10

    12
    OnNetwork+: Network Delay-Aware Management for Mobile Systems

    Kim, Hyeonggyu; Ju, Minho; Kim, Soontaeresearcher, ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, v.17, no.3, pp.64:1 - 64:23, 2018-06

    13
    TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption

    Kim, Jesung; Lee, Jongmin; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.7, pp.1200 - 1211, 2017-07

    14
    Write-Amount-Aware Management Policies for STT-RAM Caches

    Kim, Hyeonggyu; Kim, Soontaeresearcher; Lee, Jooheung, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.4, pp.1588 - 1592, 2017-04

    15
    A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption

    Park, Jungwoo; Lee, Jongmin; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.25, no.3, pp.793 - 805, 2017-03

    16
    Smart ECC Allocation Cache Utilizing Cache Data Space

    Hong, Jeongkyu; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.2, pp.368 - 374, 2017-02

    17
    Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches

    Farbeh, Hamed; Kim, Hyeonggyu; Miremadi, Seyed Ghassem; et al, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.12, pp.3661 - 3675, 2016-12

    18
    RAMS: DRAM Rank-Aware Memory Scheduling for Energy Saving

    Lee, Yebin; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.3210 - 3216, 2016-10

    19
    Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures

    Hong, Seokin; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.2999 - 3012, 2016-10

    20
    Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches

    Hong, Jeongkyu; Kim, Soontaeresearcher, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.6, pp.2152 - 2164, 2016-06

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