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Showing results 1 to 8 of 8

1
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC

Chung, Jae-Hyun; Kim, Ye-Dam; Park, Chang-Un; Park, Kun-Woo; Oh, Dong-Ryeol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.59, no.8, pp.2481 - 2491, 2024-08

2
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation

Kim, Jong-In; Oh, Dong-Ryeol; Jo, Dong Shin; Sung, Ba-Ro-Saim; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.10, pp.2319 - 2330, 2015-10

3
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8x Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration

Oh, Dong-Ryeol; 김종인; Jo, Dong-Shin; Kim, Woo-Cheol; Chang, Dong-Jin; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.1, pp.288 - 297, 2019-01

4
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

Oh, Dong-Ryeol; Seo, Min-Jae; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2791 - 2801, 2022-09

5
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

Oh, Dong-Ryeol; Moon, Kyoung-Jun; Lim, Won-Mook; Kim, Ye-Dam; An, Eun-Ji; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.4, pp.1216 - 1226, 2021-04

6
An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers

Oh, Dong-Ryeol; Moon, Kyoung-jun; Lim, Won-mook; Kim, Yedam; An, Eun-ji; Ryu, Seung-Tak, Symposium on VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-10

7
Power-efficient flash ADC with complementary voltage-to-time converter

Oh, Dong-Ryeol; Jo, Dong Shin; 문경준; Roh, Yi-Ju; Ryu, Seung-Tak, ELECTRONICS LETTERS, v.53, no.12, pp.772 - +, 2017-06

8
Time-domain interpolation technique for low-power time-interleaved ADC = 저전력 시분할 아날로그/디지털 변환기를 위한 시간 영역 인터폴레이션 기법link

Oh, Dong-Ryeol; Ryu, Seung-Tak; et al, 한국과학기술원, 2019

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