Power-efficient flash ADC with complementary voltage-to-time converter

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A power-efficient complementary voltage-to-time converter (CVTC) is proposed for a flash ADCs. The alternating reset direction according to the signal development direction reduces the power consumed by the reset operation and the operational frequency of the CVTC is effectively reduced by half. Accordingly, the logic circuits following the CVTC work in a time-interleaved manner, resulting in significant power saving. A 5-bit 2.5 GS/s flash ADC designed for a 40 nm CMOS process shows a 27% power reduction over the conventional voltage-to-time conversion-based flash ADC.
Publisher
INST ENGINEERING TECHNOLOGY-IET
Issue Date
2017-06
Language
English
Article Type
Article
Citation

ELECTRONICS LETTERS, v.53, no.12, pp.772 - +

ISSN
0013-5194
DOI
10.1049/el.2017.1287
URI
http://hdl.handle.net/10203/224882
Appears in Collection
EE-Journal Papers(저널논문)
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