Showing results 152821 to 152840 of 203751
VERIFICATION METHOD FOR THE FBD-STYLE DESIGN SPECIFICATION USING SDT AND SMV Song, Myung Jun; Koo, Seo Ryong; Seong, Poong-Hyun, SE2004, 2004-02 |
Verification Methodology for Simulation Model based on System Morphism Choi, Chang-Beom; Kim, Tag-Gon, DHSS‘ 2011, DHSS, 2011-09 |
Verification methodology of compatible microprocessors Yim, JS; Park, CJ; Yang, WS; Oh, HS; Lee, HC; Choi, H; Kim, TH; et al, Proceedings of the 1997 Asia and South Pacific Design Automation Conference, ASP-DAC, pp.173 - 180, 1997-01-28 |
Verification of A Microprocessor Using Real World Applications Chang, Y.S.; Lee, S.J.; Kyung, Chong-Min; Park, In-Cheol, IEEE International High Level Design Validation and Test Workshop(HLDVT'98), pp.204 - 210, IEEE, 1998-11 |
Verification of a Microprocessor Using Real World Applications Chang, Y.S.; Lee, S.J.; Park, In-Cheol; Kyung, Chong-Min, The 36th Design Automation Conference(DAC), pp.181 - 184, The 36th Design Automation Conference(DAC), 1999-06 |
Verification of correlated errors in noisy quantum measurements with NISQ devices = NISQ 장치를 이용한 잡음 섞인 양자 측정의 상관 오류 검증link Seo, Seungchan; Bae, Joonwoo; et al, 한국과학기술원, 2022 |
Verification of Directed Self-Assembly (DSA) Guide Patterns through Machine Learning Shim, Seongbo; Cai, Sibo; Yang, Seunghune; Choi, Jungdal; Shin, Youngsoo, Conference on Alternative Lithographic Technologies VII, SPIE, 2015-02-26 |
Verification of electrodeposition behavior of Ce(III) in terms of its empirical formula in high temperature molten LiCl-KCl = 고온 LiCl-KCl 용융염 내 Ce(III)의 전착예측 실험상관식 개발을 통한 전착거동 규명link Jee, Young Taek; Yun, Jong-Il; et al, 한국과학기술원, 2019 |
Verification of Engineering Assumptions in Modeling of Airborne Release of Carbon-14 Scott A. Simonson; Yim Man-Sung, 1996 Electric Power Research Institute International LLW Conference, no.1996, pp.203 - 214, EPRI, 1996-07 |
Verification of finite state machine using temporal logic specification = 시간논리 사양으로 주어진 유한상태 Machine 의 검증link Jeong, Seh-Woong; 정세웅; et al, 한국과학기술원, 1987 |
Verification of function block diagram through verilog translation = Verilog 변환을 이용한 FBD의 정형검증link Jeon, Seung-Jae; 전승재; et al, 한국과학기술원, 2007 |
Verification of Gas System Analysis Code GAMMA+ with S-CO2 Compressor Test Data 배성준; 안윤한; 이정익, 2015 한국원자력학회 춘계학술대회, 한국원자력학회, 2015-05-07 |
Verification of Graphemes Using Neural Networks for HMM-Based On-line Handwritten Hangul Syllable Recognition Kim, JinHyung; Cho, SJ, Proceeding of the First Tsinghua-KAIST Joint Workshop on Document Recognition, v.2, no.0, pp.18 - 24, International Journal of Computer Processing of Oriental Languages, 2002-03 |
VERIFICATION OF GRAPHEMES USING NEURAL NETWORKS IN AN HMM-BASED ON-LINE KOREAN HANDWRITING RECOGNITION SYSTEM CHO, SJ; KIM, J; Kim, JinHyung, The 7th Int'l Workshop on Frontiers in Handwriting Recognition, pp.219 - 228, 2000-09 |
Verification of Heat Exchanger Design Code KAIST_HXD by Experiment Baik, Seung Joon; Kim, Seong Gu; Bae, Seong Jun; Ahn, Yoon Han; Lee, Jeong Ik, The Korean Nuclear Society Autumn Meeting (2014), The Korean Nuclear Society, 2014-10-31 |
Verification of intelligent network services by analyzing feature interactions using a petri net model = 페트리네트 모델을 사용한 서비스 상호작용 분석에 의한 지능망 서비스의 검증link Choi, Jeong-Hun; 최정훈; et al, 한국과학기술원, 2003 |
Verification of Interface State Properties of a-InGaZnO Thin-Film Transistors With Sin(x) and SiO2 Gate Dielectrics by Low-Frequency Noise Measurements Choi, Hyun-Sik; Jeon, Sanghun; Kim, Hojung; Shin, Jaikwang; Kim, Changjung; Chung, U-In, IEEE ELECTRON DEVICE LETTERS, v.32, no.8, pp.1083 - 1085, 2011-08 |
Verification of Logic Gate Interconnection J.C.Jung; Kyung, Chong-Min, 전기학회논문지, v.24, no.2, pp.338 - 346, 1987-03 |
Verification of logic gate interconnection = 논리회로 상호간의 연결도 검증link Jung, Ja-Choon; 정자춘; et al, 한국과학기술원, 1986 |
Verification of Navigation System of Guided Munition by Flight Experiment 김영주; 임승한; 방효충; 김재호; 박장호, 한국항공우주학회지, v.44, no.11, pp.965 - 972, 2016-11 |
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