Verification of function block diagram through verilog translation = Verilog 변환을 이용한 FBD의 정형검증

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The formal verification of FBD program is required in nuclear engineering domain as traditional relay-based analog systems are being replaced with digital PLC based software. This paper proposes a way to formally verify the FBD program. For this purpose, Verilog model is automatically translated from the FBD program, then Cadence SMV performs model checking. We demonstrated the effectiveness of the suggested approach by conducting a case study of the nuclear reactor protection system, which is currently being developed in Korea.
Advisors
Cha, Sung-Deok차성덕
Description
한국과학기술원 : 전산학전공,
Publisher
한국과학기술원
Issue Date
2007
Identifier
265056/325007  / 020053532
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전산학전공, 2007.2, [ v, 26 p. ]

Keywords

model checking; verification; Function Block Diagram; Verilog translation; Verilog 변환; 모델체킹; 검증; FBD

URI
http://hdl.handle.net/10203/34775
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=265056&flag=dissertation
Appears in Collection
CS-Theses_Master(석사논문)
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