Browse "College of Engineering(공과대학)" by Type Conference
Showing results 1181 to 1200 of 90925
| A 1452-% power extraction improvement energy harvesting circuit with simultaneous energy extraction from a piezoelectric transducer and a thermoelectric generator Yoon, Kye-Seok; Hong, Sung-Wan; Lee, Sang-Han; Choi, Sung-Won; Cho, Gyu-Hyeong, 31st Symposium on VLSI Circuits, pp.C202 - C203, IEEE, 2017-06 |
| A 145W 88 parallel multiplier based on optimized bypassing architecture Hong, S.; Roh, T.; Yoo, Hoi-Jun, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, pp.1175 - 1178, IEEE, 2011-05-15 |
| A 146.52 TOPS/W Deep-Neural-Network Learning Processor with Stochastic Coarse-Fine Pruning and Adaptive Input/Output/Weight Skipping Kim, Sangyeob; Yoo, Hoi-Jun; LEE, JUHYOUNG; Kang, Sanghoon; Lee, Jinmook, IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Institute of Electrical and Electronics Engineers Inc., 2020-06-16 |
| A 148fsrms Integrated Noise 4MHz Bandwidth All-Digital Second-Order ΔΣ Time-to-Digital Converter Using Gated Switched-Ring Oscillator Yu, Wonsik; Kim, KwangSeok; Cho, SeongHwan, 2013 IEEE Custom Integrated Circuits Conference - CICC, pp.1 - 4, IEEE, 2013-09-25 |
| A 14b-linear capacitor self-trimming pipelined ADC Ryu, Seung-Tak; Ray, S.; Song, B.-S.; Cho, G.-H.; Bacrania, K., Digest of Technical Papers - 2004 IEEE International Solid-State Circuits Conference, v.47, pp.464 - 0, 2003-02-15 |
| A 15.2 TOPS/W CNN accelerator with similar feature skipping for face recognition in mobile devices Kim, Sangyeob; Lee, Juhyoung; Kang, Sanghoon; Lee, Jinsu; Yoo, Hoi-Jun, 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-05 |
| A 150MHz 8-Banks 256M Synchronous DRAM with the Wave Pipelining Method Yoo, Hoi-Jun, 95 IEEE Int. Solid State Circuit Conf., 1995 |
| A 152mW mobile multimedia SoC with fully programmable 3D graphics and MPEG4/H.264/JPEG Woo, J.-H.; Sohn, J.-H.; Kim, H.; Jeong, J.; Jeong, E.; Lee, S.J.; Yoo, Hoi-Jun, 2007 Symposium on VLSI Circuits, VLSIC, pp.220 - 221, 123, 2007-06-14 |
| A 152mW/195mW Multimedia Processor with Fully Programmable 3D Graphics and MPEG/H.264/JPEG for Handheld Devices Yoo, Hoi-Jun; Woo, Jeong-Ho; Sohn, Ju-Ho; Kim, Hyejung; Jeong, Jongcheol; Jeong, Euljoo; Lee, Suk Joong, Design Automation Conference(DAC), 2007 |
| A 159.2mW SoC implementation of T-DMB receiver including stacked memories Lee, J.; Kim, S.; Kim, J.; Kim, D.; Kwon, Y.; Choi, M.; Park, K.; et al, IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.679 - 682, IEEE, 2008-09-21 |
| A 15μW 16 channel ExG processor with data transition memory-quad level vector for wearable healthcare platform Roh, Taehwan; Lee, SeulKi; Yoo, Hoi-Jun, IEEE Biomedical Circuits and Systems -BioCAS 2011, pp.325 - 328, IEEE, 2011-11-11 |
| A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation Ha, Sohmyung; Akinin, Abraham; Park, Jiwoong; Kim, Chul; Wang, Hui; Maier, Christoph; Cauwenberghs, Gert; et al, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, pp.C106 - C107, Institute of Electrical and Electronics Engineers Inc., 2015-06 |
| A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks Jo, Wooyoung; Kim, Sangjin; Lee, Juhyoung; Um, Soyeon; Li, Zhiyong; Yoo, Hoi-Jun, 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022, pp.365 - 369, Institute of Electrical and Electronics Engineers Inc., 2022-05 |
| A 17.5 fJ/bit Energy-efficient Analog SRAM for Mixed-signal Processing Yoo, Hoi Jun; Lee, Jinsu; Shin, Dongjoo; Kim, Youchang, IEEE International Symposium on Circuit and Systems, IEEE, 2016-05 |
| A 170MHz-Lock-In-Range and-253dB-FoM(jitter), 12-to-14.5GHz Subsampling PLL with a 150 mu W Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator Lim, Younghyun; Kim, Juyeop; Jo, Yongwoo; Bang, Jooeun; Yoo, Seyeon; Park, Hangi; Yoon, Heein; et al, IEEE International Solid-State Circuits Conference (ISSCC), pp.280 - 282, IEEE, 2020-02-19 |
| A 17mW, 20Mpixels/s 3-D Rendering Processor For Portable Multimedia Application 유회준, ISOCC 2005, pp.612 - 613, 2005-10 |
| A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-um CMOS Seo, Min-Jae; Jin, Dong-Hwan; Kim, Ye-Dam; Hwang, Sun-Il; Kim, Jong-Pal; Ryu, Seung-Tak, International Symposium on Integrated Circuits and Systems, pp.3617 - 3627, IEEE CAS Society, 2018-09-02 |
| A 186Mvertices/s 161mW floating-point vertex processor for mobile graphics systems Yu, C.-H.; Chung, K.; Kim, D.; Kim, Lee-Sup, 2007 IEEE Custom Integrated Circuits Conference, CICC, pp.579 - 582, 2007-09-16 |
| A 187dB FoMS 46fJ/Conv. 2nd-order Highpass ΔΣ Capacitance-to-Digital Converter Jung, Yoontae; Oh, Sein; Koo, Jimin; Park, Seunga; Suh, Ji-Hoon; Cho, Donghee; Ha, Sohmyung; et al, 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), IEEE, 2023-06-11 |
| A 188fsrms-Jitter and -243d8-FoMjitter5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector Hwang, Chanwoong; Park, Hangi; Seong, Taeho; Choi, Jaehyouk, 2022 IEEE International Solid-State Circuits Conference, ISSCC 2022, pp.378 - 380, Institute of Electrical and Electronics Engineers Inc., 2022-02 |
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