A 159.2mW SoC implementation of T-DMB receiver including stacked memories

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 284
  • Download : 670
Publisher
IEEE
Issue Date
2008-09-21
Language
ENG
Citation

IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.679 - 682

ISSN
0886-5930
URI
http://hdl.handle.net/10203/12876
Appears in Collection
EE-Conference Papers(학술회의논문)
Files in This Item
A 159.2mW SoC implementation of T-DMB receiver including stacked memories.pdf(618.09 kB)Download

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0