Design of an efficient synchronizer for IEEE 802.16d systems

Abstract

A synchronizer for IEEE 802.16d system is implemented as a soft-core IP. This synchronizer does coarse time synchronization, fractional CFO estimation, fine STO estimation and integer CFO estimation, as the overall procedure proposed for IEEE 802.16d system. New architectures are proposed for each of these synchronizations. First, the separated data-paths, with each of their optimal bit-widths, are proposed for the coarse time synchronization and the fractional CFO estimation. And dual data-paths for the coarse time synchronization are proposed with the adaptive selection of them. With the proposed architecture for these synchronizations, only about 40% of the power is consumed in the coarse time synchronization in spite of about 30% reduction of the gate count. Additionally, the accuracy of fractional CFO estimation is improved without the ambiguity of the selection with the pure auto-correlation for it. Second, a new architecture for the joint estimation of fine STO and the integer CFO is proposed. This architecture presents a solution for the sensitivity of the one estimation to the error of the other. With this architecture, better performance can be achieved in entire SNR range, in on-line manner.