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Park, In-Cheol (박인철)
교수, School of Electrical Engineering(전기및전자공학부)

http://ics.kaist.ac.kr

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    NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
    1
    Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks

    Choi, Jaewoong; Kong, Byeong Yong; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.3, pp.972 - 982, 2020-03

    2
    A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access

    Kong, Byeong Yong; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.3, pp.470 - 474, 2020-03

    3
    A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis

    Kong, Byeong Yong; Lee, Jooseung; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.1, pp.166 - 176, 2020-01

    4
    Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages

    Hwang, Seokha; Moon, Seungsik; Jung, Jaehwan; et al, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS, v.66, no.11, pp.4462 - 4475, 2019-11

    5
    Modified Viterbi Scoring for HMM-Based Speech Recognition

    Jo, Jihyuck; Kim, Han-Gyu; Park, In-Cheolresearcher; et al, INTELLIGENT AUTOMATION AND SOFT COMPUTING, v.25, no.2, pp.351 - 358, 2019-06

    6
    Energy-efficient Convolution Architecture Based on Rescheduled Dataflow

    Jo, Jihyuck; Kim, Suchang; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.65, no.12, pp.4196 - 4207, 2018-12

    7
    A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading

    Kong, Byeong Yong; Park, In-Cheolresearcher, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.11, pp.3327 - 3337, 2018-11

    8
    Area-optimized Syndrome Calculation for ReedSolomon Decoder

    Lee, Youngjoo; Park, In-Cheolresearcher; Yoo, Hoyoung, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.5, pp.609 - 615, 2018-10

    9
    Hybrid Sorting Architecture for Low-latency Successive Cancellation List Decoding of Polar Codes

    Kong, Byeong Yong; Park, In-Cheolresearcher, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.5, pp.593 - 601, 2018-10

    10
    A Fast Successive Cancellation List Decoder for Polar Codes With an Early Stopping Criterion

    Kim, Daesung; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON SIGNAL PROCESSING, v.66, no.18, pp.4971 - 4979, 2018-09

    11
    Fast Low-Comlexity Triple-Error-Correcting BCH Decoding Architecture

    Kim, Daesung; Yoo, Injae; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.6, pp.764 - 768, 2018-06

    12
    Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture

    Kim, Daesung; Yoo, Injae; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.6, pp.764 - 768, 2018-06

    13
    DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks

    Jo, Jihyuck; Cha, Soyoung; Rho, Dayoung; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.2, pp.605 - 618, 2018-02

    14
    Improved Successive-Cancellation Decoding of Polar Codes Based on Recursive Syndrome Decomposition

    Choi, Jaejoon; Park, In-Cheolresearcher, IEEE COMMUNICATIONS LETTERS, v.21, no.11, pp.2344 - 2347, 2017-11

    15
    Unidirectional Ring Ethernet and Media Access Controller with Automatic Relaying for Low-complexity In-vehicle Control Network

    Yoo, Injae; Jo, Jihyuck; Ju, Youngjin; et al, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.17, no.5, pp.697 - 708, 2017-10

    16
    Low-Latency Low-Cost Architecture for Square and Cube Roots

    Jo, Jihyuck; Park, In-Cheolresearcher, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E100.A, no.9, pp.1951 - 1955, 2017-09

    17
    Improved Sorting Architecture for K-Best MIMO Detection

    Kong, Byeong Yong; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.9, pp.1042 - 1046, 2017-09

    18
    Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks

    Yoo, Injae; Park, In-Cheolresearcher, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.64, no.9, pp.1057 - 1061, 2017-09

    19
    Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion

    Lee, Youngjoo; Oh, Taehyoun; Park, In-Cheolresearcher, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.17, no.3, pp.387 - 400, 2017-06

    20
    Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems

    Jung, Jaehwan; Park, In-Cheolresearcher, IEEE COMMUNICATIONS LETTERS, v.21, no.5, pp.979 - 982, 2017-05
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