Signal integrity (SI) design and analysis of network-on-chip (NoC) of full wafer scale chip (FWSC) for ultra-large scale ai supercomputer

Abstract

In this paper, we analyzed Network-on-Chip (NoC) of the next-generation processor architecture for exascale AI supercomputers, Full Wafer Scale Chip (FWSC). We investigated the signal integrity (SI), power consumption, and latency based on the characteristics of the NoC interconnect and proposed a suitable NoC interconnect structure. The 2D mesh NoC of FWSC is designed using the conventional router structure and on-chip interconnect. Through this, we analyze the signal integrity, power consumption, and latency in the wafer-scale NoC. Additionally, we designed on-chip interconnect suitable for the wafer-scale NoC, which has a significant impact on SI, power consumption, and latency. The proposed interconnect minimizes crosstalk and capacitance by reducing the thickness of NoC signal lines and arranging adjacent signal lines diagonally. The proposed interconnect was verified by comparing it with the conventional interconnect in various aspects. As a result, the proposed interconnect outperforms the conventional