(A) 3-stage dual-residue capacitive interpolation pipelined-SAR ADC

Abstract

This work proposes a 3-stage dual-residue pipelined-SAR ADC. An interpretation of capacitive interpolation as a binary search algorithm was discussed to derive 2nd stage dual-residue generation method. By adding one stage to the conventional two-stage dual-residue pipelined structure, it is expected that the sampling rate can be increased at given clock frequency. To demonstrate implementation, simulations were configured in 28nm FDSOI process with Cadence.