(A) 3-stage dual-residue capacitive interpolation pipelined-SAR ADC세 번째 단을 갖는 이중 잔류 용량성 인터폴레이션 파이프라인 축차비교형 아날로그-디지털 변환기
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 류승탁 | - |
| dc.contributor.author | Hong, Ji-Un | - |
| dc.contributor.author | 홍지운 | - |
| dc.date.accessioned | 2024-07-30T19:31:32Z | - |
| dc.date.available | 2024-07-30T19:31:32Z | - |
| dc.date.issued | 2024 | - |
| dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1097188&flag=dissertation | en_US |
| dc.identifier.uri | http://hdl.handle.net/10203/321616 | - |
| dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2024.2,[iii, 25p. :] | - |
| dc.description.abstract | This work proposes a 3-stage dual-residue pipelined-SAR ADC. An interpretation of capacitive interpolation as a binary search algorithm was discussed to derive 2nd stage dual-residue generation method. By adding one stage to the conventional two-stage dual-residue pipelined structure, it is expected that the sampling rate can be increased at given clock frequency. To demonstrate implementation, simulations were configured in 28nm FDSOI process with Cadence. | - |
| dc.language | eng | - |
| dc.publisher | 한국과학기술원 | - |
| dc.subject | 이중 잔류 축차비교형 파이프라인 아날로그-디지털 변환기▼a데이터 컨버터▼a용량성 인터폴레이션 | - |
| dc.subject | Dual-residue pipelined-SAR ADC▼aData converter▼aCapacitive interpolation | - |
| dc.title | (A) 3-stage dual-residue capacitive interpolation pipelined-SAR ADC | - |
| dc.title.alternative | 세 번째 단을 갖는 이중 잔류 용량성 인터폴레이션 파이프라인 축차비교형 아날로그-디지털 변환기 | - |
| dc.type | Thesis(Master) | - |
| dc.identifier.CNRN | 325007 | - |
| dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
| dc.contributor.alternativeauthor | Ryu, Seung-Tak | - |
- Appears in Collection
- EE-Theses_Master(석사논문)
- Files in This Item
- There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.