(A) split time interleaved SAR ADC with sign equality based background timing skew calibration

Abstract

This paper introduces a Split Time-Interleaved SAR ADC with fully on-chip background timing mismatch calibration. The proposed design involves ADC$_{A1}$ in Part A and ADC$_{B1}$ in Part B, each operating as a reference ADC from the other Part. Additionally, to correct timing skew, a sign equality based calibration technique is employed using the reference slope (r$_{sign}$) of adjacent channels and the error value (e$_{sign}$) with the reference ADC. This calibration technique is implemented with using simple logic gates, reducing area overhead and enabling on-chip implementation. By utilizing a split structure, the ADC input impedance can be maintained consistently, effectively removing calibration spurs that arise when using reference ADCs.