DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | 류승탁 | - |
dc.contributor.author | Lee, Seongmin | - |
dc.contributor.author | 이성민 | - |
dc.date.accessioned | 2024-07-30T19:31:26Z | - |
dc.date.available | 2024-07-30T19:31:26Z | - |
dc.date.issued | 2024 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=1096803&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/321585 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2024.2,[i, 27 p. :] | - |
dc.description.abstract | This paper introduces a Split Time-Interleaved SAR ADC with fully on-chip background timing mismatch calibration. The proposed design involves ADC$_{A1}$ in Part A and ADC$_{B1}$ in Part B, each operating as a reference ADC from the other Part. Additionally, to correct timing skew, a sign equality based calibration technique is employed using the reference slope (r$_{sign}$) of adjacent channels and the error value (e$_{sign}$) with the reference ADC. This calibration technique is implemented with using simple logic gates, reducing area overhead and enabling on-chip implementation. By utilizing a split structure, the ADC input impedance can be maintained consistently, effectively removing calibration spurs that arise when using reference ADCs. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | 시분할▼a아날로그-디지털 변환기▼a부호 동일 기반의 시지연 조절 | - |
dc.subject | Time-interleaved▼aAnalog-to-digital converter▼aSign equality based timing mismatch calibration | - |
dc.title | (A) split time interleaved SAR ADC with sign equality based background timing skew calibration | - |
dc.title.alternative | 부호 동일 기반의 타이밍 스큐 보정 기법을 가지는 Split 시분할 축차비교형 아날로그 디지털 변환기 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | Ryu, Seung-Tak | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.