Study on the charge trap flash-based synaptic device for high-speed, low-power, and highly reliable neuromorphic computing

Abstract

In the hardware-based neuromorphic computing, synaptic devices play a key role for accelerating the computing. While the use of CMOS circuits can be used as synaptic device, it is ineffective in terms of power and area efficiency due to need of large number of transistors. Therefore, many researches have been studied with various single devices as synaptic device. Two-terminal devices such as memristors based on RRAM, PCM, and three-terminal devices such as electrolyte-gated FET, floating-gate FET, and ferroelectric FET, have been demonstrated as synaptic devices. Among these devices, the charge trap flash memory-based devices can be the promising synaptic device due to their CMOS compatibility and excellent reliability. However, there are known disadvantages of charge trap flash memory in terms of endurance and non-linear conductance modulation with identical pulses. In this work, we demonstrated a silicon-on-insulator charge-trap flash-based synaptic transistor using trap level engineered $Al_2O_3/Ta_2O_5/Al_2O_3$ gate stack for neuromorphic computing. This novel gate stack provided very precise control of the channel conductance with more than 6-bits. To achieve this, we measured the electronic band structure of the oxides. Then, using quasi-static split C-V technique, we verified the charge trapping/de-trapping behavior in the gate oxide. Based on this measurement, we chose the appropriate bias condition for highly linear and symmetric potentiation/depression of channel conductance. Finally, we realized the linear and symmetric conductance update with very short (25 ns) identical pulses at low voltage (< 5 V), resulting in low power consumption, long retention, and high endurance. Finally, we achieved high learning accuracy in the training of 60,000 MNIST images.