An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation

Abstract

Pipelined-SAR ADCs have proved their capability in achieving high-speed and high-resolution with excellent energy-efficiency. The well-known design burden of residue amplifier (RA) such as power-hungry opamp or calibration complexity for inaccurate open-loop amplifier could be eliminated by the single-amplifier dual-residue pipelined architecture which requires neither accurate gain nor gain matching, thereby allowing a calibration-free open-loop RA [1]–[2]. However, the high power consumption of the current-mode interpolation in [1] and the noise-coupling sensitive capacitive interpolation due to the excessive floating capacitors in [2] become additional design issues. For a low-power and noise-coupling-immune structure, this paper proposes a nonbinary capacitive interpolation technique for a single amplifier dual-residue pipelined-SAR ADC.