Highly linear SOI LDMOS power amplifier with combinated cascode structure

Abstract

A fully on-chip SOI LDMOS linear PA for WLAN is implemented in a SOI LDMOS process. A cascode of SOI CMOS and SOI LDMOS is used to overcome the breakdown issue of the SOI CMOS transistor. An adaptive power cell (APC) and specially designed CG bias network are adopted to achieve linear performance. This proposed PA has gain of 24.3 dB and output power of 20.2 dBm for an 802.11n modulated signal with the EVM of -25dB.