DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jeong, Gwanghyeon | ko |
dc.contributor.author | Joo, Taehwan | ko |
dc.contributor.author | Hong, Songcheol | ko |
dc.date.accessioned | 2017-12-05T02:44:12Z | - |
dc.date.available | 2017-12-05T02:44:12Z | - |
dc.date.created | 2017-11-29 | - |
dc.date.created | 2017-11-29 | - |
dc.date.issued | 2016-08 | - |
dc.identifier.citation | 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 | - |
dc.identifier.uri | http://hdl.handle.net/10203/227760 | - |
dc.description.abstract | A fully on-chip SOI LDMOS linear PA for WLAN is implemented in a SOI LDMOS process. A cascode of SOI CMOS and SOI LDMOS is used to overcome the breakdown issue of the SOI CMOS transistor. An adaptive power cell (APC) and specially designed CG bias network are adopted to achieve linear performance. This proposed PA has gain of 24.3 dB and output power of 20.2 dBm for an 802.11n modulated signal with the EVM of -25dB. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Highly linear SOI LDMOS power amplifier with combinated cascode structure | - |
dc.type | Conference | - |
dc.identifier.wosid | 000392495700062 | - |
dc.identifier.scopusid | 2-s2.0-84994765393 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 2016 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2016 | - |
dc.identifier.conferencecountry | CH | - |
dc.identifier.conferencelocation | Howard International House, Taipei | - |
dc.identifier.doi | 10.1109/RFIT.2016.7578175 | - |
dc.contributor.localauthor | Hong, Songcheol | - |
dc.contributor.nonIdAuthor | Jeong, Gwanghyeon | - |
dc.contributor.nonIdAuthor | Joo, Taehwan | - |
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