A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS

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This brief presents a power-efficient forwarded-clock receiver that is tolerant to high-frequency jitter by mixing filtered clock jitter to data. Due to mixing the filtered clock jitter, the proposed receiver does not include power-hungry delay lines but a phase interpolator, which enables saving significant power consumption. In a prototype receiver implemented in a 1-V 65-nm complementary metal-oxide-semiconductor process, it removes 2-GHz 0.7UI jitter modulated in data by an amount of 22%. It achieves 10 Gb/s with 0.71 pJ/bit in 10-cm FR4 channels and occupies 0.012 mm(2).
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2016-03
Language
English
Article Type
Article
Keywords

65 NM CMOS

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.3, pp.264 - 268

ISSN
1549-7747
DOI
10.1109/TCSII.2015.2482400
URI
http://hdl.handle.net/10203/208788
Appears in Collection
EE-Journal Papers(저널논문)
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