Browse "School of Electrical Engineering(전기및전자공학부)" by Author Kim, Wan
Showing results 1 to 12 of 12
| A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI- SAR) ADC Kim, Wan; Hong, Hyeok-Ki; Roh, Yi-Ju; Kang, Hyun-Wook; Hwang, Sun-Il; Jo, Dong Shin; Chang, Dong-Jin; et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.8, pp.1826 - 1839, 2016-08 |
| A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS Kim, Jong-In; Sung, Ba-Ro-Saim; Kim, Wan; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.48, no.6, pp.1429 - 1441, 2013-06 |
| A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure Kim, Si-Nai; Kim, Wan; Lee, Chang-Kyo; Ryu, Seung-Tak, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.12, no.3, pp.270 - 277, 2012-09 |
| A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control Hong, Hyeok-Ki; Kim, Wan; Park, Sun-Jae; Choi, Michael; Park, Ho-Jin; Ryu, Seung-Tak, 2012 IEEE Custom Integrated Circuits Conference, IEEE, 2012-09-10 |
| A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS Moon, Kyoung-Jun; Jo, Dong-Shin; Kim, Wan; Choi, Michael; Ko, Hyung-Jong; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2532 - 2542, 2019-09 |
| A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC Hong, Hyeok-Ki; Kim, Wan; Kang, Hyunwook; Park, Sun-Jae; Choi, Michael; Park, Ho-Jin; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.2, pp.543 - 555, 2015-02 |
| A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design Lee, Chang-Kyo; Kim, Wan; Kang, Hyun-Wook; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.60, no.9, pp.557 - 561, 2013-09 |
| A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks Seo, Min-Jae; Roh, Yi-Ju; Chang, Dong-Jin; Kim, Wan; Kim, Ye-Dam; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.65, no.12, pp.1904 - 1908, 2018-12 |
| A time-domain latch interpolation technique for low power flash ADCs Kim, Join-In; Kim, Wan; Sung, Barosaim; Ryu, Seung-Tak, 2011 IEEE Custom Integrated Circuits Conference, IEEE, 2011-09-20 |
| A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme Kang, Hyun-Wook; Hong, Hyeok-Ki; Kim, Wan; Ryu, Seung-Tak, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.9, pp.2584 - 2594, 2018-09 |
| Low-noise time-interleaved SAR ADC for low-supply voltage applications = 저 전압 응용을 위한 저 잡음 시-병렬 축차 비교형 아날로그-디지털 변환기link Kim, Wan; 김완; et al, 한국과학기술원, 2016 |
| Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC Chang, Dong-Jin; Kim, Wan; Seo, Min-Jae; Hong, Hyeok-Ki; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.64, no.2, pp.322 - 332, 2017-02 |
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