A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme

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This paper presents a two-way time-interleaved (TI) 12-b 270-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a virtual-timing-reference timing-skew calibration scheme, in which the timing-skew calibration spurs present in conventional calibration schemes are effectively suppressed with the deferred reference sampling edge. The proposed design runs in a true background mode of operation, whose accuracy is independent of the statistics and the wide-sense stationary property of the input. A 12-b 270-MS/s prototype ADC with the on-chip timing-skew and offset calibration circuits is fabricated in a 40-nm CMOS process, where the timing-skew calibration circuits occupy only 9.7% of the total core area, showing the simplicity and ease of integration of the calibration algorithm even in large-scale TI ADCs. The prototype achieves a peak SNDR of 60.2 dB and a Nyquist-rate SNDR of 59.7 dB while consuming 4.5 mW from a 0.9-V supply, which then results in a Walden FoM of 21.1 fJ/conversion-step.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2018-09
Language
English
Article Type
Article
Keywords

NM CMOS

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.53, no.9, pp.2584 - 2594

ISSN
0018-9200
DOI
10.1109/JSSC.2018.2843360
URI
http://hdl.handle.net/10203/245891
Appears in Collection
EE-Journal Papers(저널논문)
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