Showing results 1 to 46 of 46
A Consideration of DRAM Power Management Effect on Energy Consumption Lee, Yebin; Kim, Soontae, Triangle Symposium on Advanced ICT, 2009-10-29 |
Adopting TLB Index-based Tagging to Data Caches for Tag Energy Reduction Lee, Jongmin; Kim, Soontae, ACM/IEEE International Symposium on Low Power Electronics and Design, pp.231 - 236, ACM/IEEE, 2012-07-31 |
An energy-delay efficient 2-level data cache architecture for embedded system Lee, Jongmin; Kim, Soontae, 2009 ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED'09, pp.343 - 346, IEEE-CAS and ACM-SIGDA, 2009-08-19 |
Area-Efficient Error Protection for Caches Kim, Soontae, Design Automation and Test in Europe Conference, v.1, pp.1 - 6, 2006-03 |
AVICA: An Access-time Variation Insensitive L1 Cache Architecture Hong, Seokin; Kim, Soontae, 2013 Design Automation and Test in Europe Conference(DATE), pp.65 - 70, European Design and Automation Association (EDAA), 2013-03-19 |
Control Flow Error Protection by Selective Re-execution and Available Redundancies in the Pipeline Rouf M.A.; Kim, Soontae, International Exposition Yeosu Korea, International Conference on Information Technology (YSEC 2012), 한국정보처리학회, 2012-04-27 |
DRAM energy reduction by prefetching-based memory traffic clustering Lee, Yebin; Kim, Soontae, 21st Great Lakes Symposium on VLSI, GLSVLSI 2011, pp.103 - 108, SIGDA, 2011-05-02 |
DRAM Power-Aware Rank Scheduling Kim, Sukki; Kim, Soontae; Lee, Yebin, ACM/IEEE International Symposium on Low Power Electronics and Design, pp.397 - 402, ACM/IEEE, 2012-08-01 |
EAR: ECC-Aided Refresh Reduction through 2-D Zero Compression Jeongkyu Hong; Kim, Hyeonggyu; Kim, Soontae, 27th International Conference on Parallel Architectures and Compilation Techniques (PACT'18), pp.1 - 11, Institute of Electrical and Electronics Engineers Inc., 2018-11-01 |
ECC string: Flexible ECC management for low-cost error protection of L2 caches Hong, Jeongkyu; Kim, Soontae, 30th IEEE International Conference on Computer Design (ICCD), pp.175 - 180, IEEE Circuits and Systems Society, 2012-09-30 |
Efficient memory reclaiming for mitigating sluggish response in mobile devices Ju, Minho; Kim, Hyeonggyu; Kang, Mincheol; Kim, Soontae, IEEE International Conference on Consumer Electronics - Berlin, pp.232 - 236, IEEE, 2015-09-07 |
ENCORE Compression: Exploiting Narrow-width Values for Quantized Deep Neural Networks Jang, Myeongjae; Kim, Jinkwon; Kim, Jesung; Kim, Soontae, 25th Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.1503 - 1508, IEEE, 2022-03 |
Energy Behavior of Java Applications from the Memory Perspective Vijaykrishnan, N.; Kandemir, M.; Kim, Soontae; Tomar, S.; Sivasubramaniam, A.; Irwin, M. J., USENIX Java Virtual Machine Research and Technology Symposium, pp.207 - 220, 2001-04-01 |
Energy-efficient batch scheduling for background network services in mobile devices Ju, Minho; Kim, Hyeonggyu; Kim, Soontae, IEEE International Conference on Consumer Electronics, IEEE, 2016-01-10 |
Energy-Efficient Instruction Cache Using Page-Based Placement Kim, Soontae; Vijaykrishnan, N.; Kandemir , M.; Irwin, M. J., International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pp.229 - 237, 2001-11-01 |
Exploiting Inter-block Entropy to Enhance the Compressibility of Blocks with Diverse Data kim, Jinkwon; Kang, Mincheol; Hong, Jeongkyu; Kim, Soontae, 28th Annual IEEE International Symposium on High-Performance Computer Architecture (HPCA), pp.1100 - 1114, IEEE COMPUTER SOC, 2022-04 |
Fine-grained fault tolerance for process variation-aware caches Mahmood T.; Kim, Soontae, IEEE Annual Symposium on VLSI, ISVLSI 2010, pp.46 - 51, 2010-07-05 |
HARP: Hardware-Based Pseudo-Tiling for Sparse Matrix Multiplication Accelerator Kim, Jinkwon; Jang, Myeongjae; Nam, Haejin; Kim, Soontae, 56th IEEE/ACM International Symposium on Microarchitecture (MICRO 2023), IEEE(Computer Society), 2023-11-01 |
High definition video transmission using bluetooth over UWB Lee, Sangjae; Lee, Seonghee; Jeon, Youngae; Choi , Sangsung; Kim, Soontae, 2010 International Conference on Consumer Electronics, ICCE 2010, pp.85 - 86, 2010-01-11 |
Leveraging intra-page update diversity for mitigating write amplification in SSDs Fareed, Imran; Kang, Mincheol; Lee, Wonyoung; Kim, Soontae, 34th ACM International Conference on Supercomputing, ICS 2020, Association for Computing Machinery, 2020-07-01 |
Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU Hong, Seokin; Kim, Soontae, 28th IEEE International Conference on Computer Design, ICCD 2010, pp.342 - 349, 2010-10-03 |
Low-cost Control Flow Error Protection by Exploiting Available Redundancies in the Pipeline Rouf M.A.; Kim, Soontae, Asia and South Pacific Design Automation Conference, pp.175 - 180, ACM SIGDA, IEEE Circuits and Systems Society, 2012-01-31 |
Macho: A Failure Model-oriented Adaptive Cache Architecture to enable Near-Threshold Voltage Scaling Tayyeb Mahmood; Kim, Soontae; Hong, Seokin, IEEE International Symposium on High Performance Computer Architecture , pp.532 - 541, IEEE Computer Society, 2013-02-27 |
Masking the energy behavior of DES encryption [smart cards] Saputra, H.; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J.; Brooks, R.; Kim, Soontae, Design Automation and Test in Europe Conference, pp.84 - 89, 2003-03-01 |
Modeling and evaluation of control flow vulnerability in the embedded system Rouf, M.A.; Kim, Soontae, 18th Annual IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2010, pp.430 - 433, 2010-08-17 |
MofySim: A mobile full-system simulation framework for energy consumption and performance analysis Ju, Minho; Kim, Hyeonggyu; Kim, Soontae, 17th International Symposium on Performance Analysis of Systems and Software, ISPASS 2016, pp.245 - 254, IEEE Computer Society, 2016-04-19 |
Near-Threshold Voltage Scaling in Last level Caches Tayyeb Mahmood; Kim, Soontae, International Exposition Yeosu Korea, International Conference on Information Technology (YSEC 2012), 한국정보처리학회, 2012-04-27 |
Network delay-aware energy management for mobile systems Ju, Minho; Kim, Hyeonggyu; Kim, Soontae, Design, Automation & Test in Europe Conference & Exhibition, European Design and Automation Association (EDAA), 2016-03-14 |
On Load Latency in Low-Power Caches Kim, Soontae; Vijaykrishnan, N.; Irwin, M.J.; John, L.K., Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. (ISLPED '03) , pp.258 - 261, 2003-08-01 |
PAPA: Partial Page-aware Page Allocation in TLC Flash SSD for Performance Enhancement Imran, Fareed; Kang, Mincheol; Lee, Wonyoung; Kim, Soontae, 36th International Conference on Massive Storage Systems and Technology, MSST 2020, Santa Clara University, 2020-10-29 |
Partial Row Activation for Low-Power DRAM System Lee, Yebin; Kim, Hyeonggyu; Hong, Seokin; Kim, Soontae, IEEE International Symposium on High Performance Computer Architecture, pp.217 - 228, IEEE Computer Society, 2017-02-06 |
Performance Controllable Shared Cache Architecture for Multi-Core Soft Real-Time Systems Lee, Myoungjun; Kim, Soontae, IEEE International Conference on Computer Design, pp.519 - 522, IEEE, 2013-10-07 |
Performance modeling using hardware performance counters Kim, Soontae, Triangle Symposium on Advanced ICT, 2010-01-25 |
Power-aware Partitioned Cache Architectures Kim, Soontae; Kandemir, M.; Sivasubramaniam, A.; Irwin, M.J.; Geethanjali, E., ACM/IEEE International Symposium on Low Power Electronics and Design, pp.64 - 67, 2001-08 |
Predictive Precharging for Bitline Leakage Energy Reduction Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., 15th Annual IEEE International ASIC/SOC Conference, 2002. , pp.36 - 40, 2002-09 |
Reducing ALU and Register File Energy by Dynamic Zero Detection Kim, Soontae, International Performance Computing and Communication Conference, pp.365 - 371, IEEE Internationa Performance, Computing, and Communications Conference, 2007. (IPCCC 2007), 2007-04 |
Resuscitating Privacy-Preserving Mobile Payment with Customer in Complete Control Konidala, Divyan M.; Dwijaksara, Made H; Kim, Kwangjo; Lee, Dongman; Lee, Byoungcheon; Kim, Daeyoung; Kim, Soontae, International Workshop on Smartphone Applications and Services, 2010-12-09 |
Salvaging Runtime Bad Blocks by Skipping Bad Pages for Improving SSD Performance Moon, Junoh; Kang, Mincheol; Lee, Wonyoung; Kim, Soontae, 25th Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.576 - 579, IEEE, 2022-03 |
Scheduling Reusable Instructions for Power Reduction Hu, J.S.; Vijaykrishnan, N.; Kim, Soontae; Kandemir, M.; Irwin, M.J., Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004. , v.1, pp.148 - 153, 2004-02 |
SimTag: Exploiting tag bits similarity to improve the reliability of the data caches Kim, Jesung; Kim, Soontae; Lee, Yebin, Design, Automation and Test in Europe Conference and Exhibition, DATE 2010, pp.941 - 944, 2010-03-08 |
Skinflint DRAM System: Minimizing DRAM Chip Writes for Low Power Lee, Yebin; Kim, Soontae; Hong, Seokin; Lee, Jongmin, IEEE International Symposium on High Performance Computer Architecture , pp.25 - 34, IEEE Computer Society, 2013-02-23 |
TEPS: Transient error protection utilizing sub-word parallelism Hong, Seokin; Kim, Soontae, 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, pp.286 - 291, 2009-05-14 |
Ternary Cache: Three-valued MLC STT-RAM Caches Hong, Seokin; Lee, Jongmin; Kim, Soontae, IEEE International Conference on Computer Design, IEEE Circuits and Systems Society, 2014-10-20 |
TLB Index-based Tagging for Cache Energy Reduction Lee, Jongmin; Hong, Seokin; Kim, Soontae, ACM/IEEE International Symposium on Low Power Electronics and Design, pp.85 - 90, IEEE-CAS and ACM-SIGDA, 2011-08-01 |
Use of local memory for efficient Java execution Tomar, S.; Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., IEEE International Conference on Computer Design, pp.468 - 473, 2001-09 |
Write buffer-oriented energy reduction in the L1 data cache of two-level caches for the embedded system Kim, Soontae; Lee, Jongmin, 20th Great Lakes Symposium on VLSI, GLSVLSI 2010, pp.257 - 262, 2010-05-16 |
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