EAR: ECC-Aided Refresh Reduction through 2-D Zero Compression

Abstract

Continuous DRAM scaling and integration is making refresh operations not scalable because more rows have to be refreshed in the same refresh interval. Thus, refresh operations are expected to consume more power in future DRAMs. To alleviate this problem, we propose a compression-based refresh-reducing DRAM architecture. To exploit prevalent zero and small memory values, we devise a novel 2-D ZERO compression scheme to increase compression coverage significantly with simple hardware support. 2-D ZERO compression can achieve 77% compression coverage compared to 50% of the conventional zero-value compression. The freed space of memory blocks obtained by 2-D zero compression is exploited to store ECC bits, which can correct bit-errors that occur when the refresh interval is lengthened to reduce refresh operations. Experimental results show that more than 98% of refresh operations can be removed and overall DRAM power consumption is reduced by 9%.