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A 9 bit, 1.12 ps Resolution 2.5 b/ Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register Kim, KwangSeok; Yu, Wonsik; Cho, SeongHwan, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.4, pp.1007 - 1016, 2014-04 |
A Second-Order Delta Sigma Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits Kim, Dongin; Kim, Kwangseok; Yu, Wonsik; Cho, Seonghwan, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.10, pp.1643 - 1647, 2019-10 |
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