A Second-Order Delta Sigma Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits

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In this brief, time-domain arithmetic circuits, such as time adder, time subtractor, and time integrator, are proposed. The concept of these time-domain circuits are explained and their non-idealities are analyzed. Using the proposed time-domain arithmetic circuits, a prototype second-order Delta Sigma-time-to-digital converter is implemented in a 65 nm standard CMOS process. The fabricated chip achieves 1.44 ps(rms) of integrated noise in 1-MHz bandwidth while consuming 3.5 mW at 50 MS/s.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2019-10
Language
English
Article Type
Article; Proceedings Paper
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.66, no.10, pp.1643 - 1647

ISSN
1549-7747
DOI
10.1109/TCSII.2019.2925860
URI
http://hdl.handle.net/10203/268107
Appears in Collection
EE-Journal Papers(저널논문)
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