A Second-Order Delta Sigma Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits

Abstract

In this brief, time-domain arithmetic circuits, such as time adder, time subtractor, and time integrator, are proposed. The concept of these time-domain circuits are explained and their non-idealities are analyzed. Using the proposed time-domain arithmetic circuits, a prototype second-order Delta Sigma-time-to-digital converter is implemented in a 65 nm standard CMOS process. The fabricated chip achieves 1.44 ps(rms) of integrated noise in 1-MHz bandwidth while consuming 3.5 mW at 50 MS/s.