A 9 bit, 1.12 ps Resolution 2.5 b/ Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

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In this paper, a 2.5 b/ stage pipelined time- to- digital converter ( TDC) is presented. For pipelined operation, a novel time- register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse- train time- amplifier, a 9- bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/ stage TDCs and a 3 b delay- line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/ s while consuming 15.4 mW. Compared to other high- resolution state- of- the- art TDCs, the proposed pipelined TDC achieves the best figure- of- merit ( FoM) without any calibration. I
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2014-04
Language
English
Article Type
Article; Proceedings Paper
Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.49, no.4, pp.1007 - 1016

ISSN
0018-9200
DOI
10.1109/JSSC.2013.2297412
URI
http://hdl.handle.net/10203/188943
Appears in Collection
EE-Journal Papers(저널논문)
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