A Unified Graphics and Vision Processor With a 0.89 mu W/fps Pose Estimation Engine for Augmented Reality

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A unified vision and graphics processor with three layers is shown to provide a fast pipeline for augmented reality. In the image-level layer, a 153.6 GOPS massively parallel processing unit with eight SIMD processors, each containing 128 processing elements, performs highly data-parallel operations. In the sub-image layer, a rasterizer and a pixel arranger respectively generate and reduce data-level parallelism. In the descriptor-level layer, a pose estimation engine executes sequential programs. Our processor can provide images for augmented reality at 100 fps, for a power consumption of 413 mW. This is 39% faster than a comparable smartphone implementation. Our chip is fabricated in a 0.18 mu m CMOS process and contains 0.95 M gates.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2013-02
Language
English
Article Type
Article
Keywords

PARALLEL PROCESSOR; GOPS

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.21, no.2, pp.206 - 216

ISSN
1063-8210
DOI
10.1109/TVLSI.2012.2186157
URI
http://hdl.handle.net/10203/97561
Appears in Collection
EE-Journal Papers(저널논문)
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