Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors

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An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2 mu m in a test chip fabricated using 0.18 mu m CMOS process and has demonstrated fixed pattern noise less than 0.46%.
Publisher
INSTITUTION ENGINEERING TECHNOLOGY -IET
Issue Date
2006
Language
English
Article Type
Article
Keywords

ON-A-CHIP

Citation

ELECTRONICS LETTERS, v.42, no.6, pp.335 - 337

ISSN
0013-5194
DOI
10.1049/el:20064189
URI
http://hdl.handle.net/10203/88104
Appears in Collection
RIMS Journal Papers
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